RgGen::SystemVerilog

RgGen::SystemVerilog provides SystemVerilog RTL and UVM register model (UVM RAL) generators for RgGen.

Installation

During RgGen installation, RgGen::SytemVerilog will also be installed automatically.

$ gem install rggen

If you want to install RgGen::SytemVerilog only, use the command below:

$ gem isntall rggen-systemverilog

Contact

Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:

• GitHub Issue Tracker
• GitHub Discussions
• Chat Room
• Mailing List
• Mail

Copyright & License

Copyright © 2019-2024 Taichi Ishitani. RgGen::SystemVerilog is licensed under the MIT License, see LICENSE for futher details.

Code of Conduct

Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the code of conduct.