Class: RgGen::VHDL::Utility::Identifier
- Inherits:
-
SystemVerilog::Common::Utility::Identifier
- Object
- SystemVerilog::Common::Utility::Identifier
- RgGen::VHDL::Utility::Identifier
- Defined in:
- lib/rggen/vhdl/utility/identifier.rb
Instance Method Summary collapse
- #__array_select__(array_index, lsb, width) ⇒ Object
- #__array_slice__(lsb, width) ⇒ Object
- #__create_select__(array_index_or_lsb, lsb_or_width, width) ⇒ Object
Instance Method Details
#__array_select__(array_index, lsb, width) ⇒ Object
17 18 19 20 21 22 23 24 |
# File 'lib/rggen/vhdl/utility/identifier.rb', line 17 def __array_select__(array_index, lsb, width) if @width lsb = __serialized_lsb__(array_index, lsb) __array_slice__(lsb, width || @width) else "(#{__serialized_index__(array_index)})" end end |
#__array_slice__(lsb, width) ⇒ Object
26 27 28 29 30 31 32 33 34 |
# File 'lib/rggen/vhdl/utility/identifier.rb', line 26 def __array_slice__(lsb, width) msb = if integer?(width) __reduce_array__([lsb, width - 1], :+, 0) else __reduce_array__([lsb, width, -1], :+, 0) end "(#{msb} downto #{lsb})" end |
#__create_select__(array_index_or_lsb, lsb_or_width, width) ⇒ Object
7 8 9 10 11 12 13 14 15 |
# File 'lib/rggen/vhdl/utility/identifier.rb', line 7 def __create_select__(array_index_or_lsb, lsb_or_width, width) if array_index_or_lsb.is_a?(Array) __array_select__(array_index_or_lsb, lsb_or_width, width) elsif lsb_or_width __array_slice__(array_index_or_lsb, lsb_or_width) else "(#{array_index_or_lsb})" end end |