Method: CPU#controller

Defined in:
lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb,
lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb

#controller ⇒ Object

Generates the bus controller.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 65

def controller
    clk,rst,req,ack = @clk,@rst,@req,@ack
    abus,dbus,rwb   = @abus,@dbus,@rwb
    allocator       = @allocator
    HDLRuby::High.cur_system.open do
        par(clk) do
            # Bus controller
            hcase(abus)
            hif(req) do
                ack <= 1
                allocator.each do |sig,addr|
                    hwhen(addr) do
                        hif(rwb) { dbus <= sig }
                        helse    { sig <= dbus }
                    end
                end
            end
            helse do
                ack <= 0
            end
        end
    end

    ## Generates a read of sig executing +ruby_block+ on the result.
    def read(sig,&ruby_block)
        addr = @allocator.get(sig)
        hif(ack == 0) do
            @abus <= addr
            @rwb <= 1
            @req <= 1
        helse
            @req <= 0
            ruby_block.call(@dbus)
        end
    end

    ## Generates a write +val+ to +sig+ executing +ruby_block+
    #  in case of success.
    def write(val,sig,&ruby_block)
        addr = @allocator.get(sig)
        hif(ack == 0) do
            @abus <= addr
            @dbus <= val
            @rwb <= 0
            @req <= 1
        helse
            @req <= 0
            ruby_block.call
        end
    end
end