Class: CPU

Inherits:
Object
  • Object
show all
Defined in:
lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb,
lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb

Overview

A generic CPU description

Direct Known Subclasses

CPUSimu, MEI8

Instance Attribute Summary collapse

Instance Method Summary collapse

Constructor Details

#initialize(dwidth, awidth, clk, rst) ⇒ CPU

Creates a new generic CPU whose data bus is +dwidth+ bit wide, address bus is +awidth+ bit wide, clock is +clk+, reset +rst+.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 30

def initialize(dwidth,awidth,clk,rst)
    # Check and set the word and address bus widths
    awidth = awidth.to_i
    dwidth = dwidth.to_i
    @awidth = awidth
    @dwidth = dwidth
    # Check and set the signals.
    @clk = clk.to_ref
    @rst = rst.to_ref
    # The allocator of the CPU
    @allocator = Allocator.new(0..(2**@addr),@data)

    # Declare the address and data buses and the
    # rwb/req/ack control signals
    abus,dbus    = nil,nil
    rwb,req,ack  = nil,nil,nil
    # Declares the data and address bus.
    HDLRuby::High.cur_system.open do
        abus = [awidth].input(HDLRuby.uniq_name)
        dbus = [dwidth].input(HDLRuby.uniq_name)
        rwb  = input(HDLRuby.uniq_name)
        req  = input(HDLRuby.uniq_name)
        ack  = output(HDLRuby.uniq_name)
    end
    @abus,@dbus    = abus,dbus
    @rwb,@req,@ack = rwb,req,ack
end

Instance Attribute Details

#abus ⇒ Object (readonly)

The address bus



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 18

def abus
  @abus
end

#ack ⇒ Object (readonly)

The acknowledge



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 26

def ack
  @ack
end

#allocator ⇒ Object (readonly)

Allocator assotiated with the bus of the CPU



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 10

def allocator
  @allocator
end

#clk ⇒ Object (readonly)

The clock.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 13

def clk
  @clk
end

#dbus ⇒ Object (readonly)

The data bus



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 20

def dbus
  @dbus
end

#req ⇒ Object (readonly)

The request



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 24

def req
  @req
end

#rst ⇒ Object (readonly)

The reset.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 15

def rst
  @rst
end

#rwb ⇒ Object (readonly)

The read/!write selection



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 22

def rwb
  @rwb
end

Instance Method Details

#connect(sig) ⇒ Object

Connect signal +sig+ to the bus allocating an address to access it.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 59

def connect(sig)
    # Allocates the signal in the address space.
    @allocator.allocate(sig)
end

#controller ⇒ Object

Generates the bus controller.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 65

def controller
    clk,rst,req,ack = @clk,@rst,@req,@ack
    abus,dbus,rwb   = @abus,@dbus,@rwb
    allocator       = @allocator
    HDLRuby::High.cur_system.open do
        par(clk) do
            # Bus controller
            hcase(abus)
            hif(req) do
                ack <= 1
                allocator.each do |sig,addr|
                    hwhen(addr) do
                        hif(rwb) { dbus <= sig }
                        helse    { sig <= dbus }
                    end
                end
            end
            helse do
                ack <= 0
            end
        end
    end

    ## Generates a read of sig executing +ruby_block+ on the result.
    def read(sig,&ruby_block)
        addr = @allocator.get(sig)
        hif(ack == 0) do
            @abus <= addr
            @rwb <= 1
            @req <= 1
        helse
            @req <= 0
            ruby_block.call(@dbus)
        end
    end

    ## Generates a write +val+ to +sig+ executing +ruby_block+
    #  in case of success.
    def write(val,sig,&ruby_block)
        addr = @allocator.get(sig)
        hif(ack == 0) do
            @abus <= addr
            @dbus <= val
            @rwb <= 0
            @req <= 1
        helse
            @req <= 0
            ruby_block.call
        end
    end
end

#read(sig, &ruby_block) ⇒ Object

Generates a read of sig executing +ruby_block+ on the result.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 89

def read(sig,&ruby_block)
    addr = @allocator.get(sig)
    hif(ack == 0) do
        @abus <= addr
        @rwb <= 1
        @req <= 1
    helse
        @req <= 0
        ruby_block.call(@dbus)
    end
end

#write(val, sig, &ruby_block) ⇒ Object

Generates a write +val+ to +sig+ executing +ruby_block+ in case of success.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb', line 103

def write(val,sig,&ruby_block)
    addr = @allocator.get(sig)
    hif(ack == 0) do
        @abus <= addr
        @dbus <= val
        @rwb <= 0
        @req <= 1
    helse
        @req <= 0
        ruby_block.call
    end
end