Class: HDLRuby::Low::SystemT

Inherits:
Object
  • Object
show all
Includes:
ForceName, Hparent, Low2Symbol
Defined in:
lib/HDLRuby/hruby_low.rb,
lib/HDLRuby/hruby_viz.rb,
lib/HDLRuby/hruby_low2c.rb,
lib/HDLRuby/hruby_low2hdr.rb,
lib/HDLRuby/hruby_low2seq.rb,
lib/HDLRuby/hruby_low2sym.rb,
lib/HDLRuby/hruby_low2vhd.rb,
lib/HDLRuby/hruby_verilog.rb,
lib/HDLRuby/hruby_low2high.rb,
lib/HDLRuby/hruby_low_cleanup.rb,
lib/HDLRuby/hruby_low_mutable.rb,
lib/HDLRuby/hruby_low_resolve.rb,
lib/HDLRuby/hruby_low_skeleton.rb,
lib/HDLRuby/hruby_low_with_var.rb,
lib/HDLRuby/hruby_low_fix_types.rb,
lib/HDLRuby/hruby_low_with_bool.rb,
lib/HDLRuby/hruby_low_with_port.rb,
lib/HDLRuby/hruby_low_bool2select.rb,
lib/HDLRuby/hruby_low_without_concat.rb,
lib/HDLRuby/hruby_low_without_select.rb,
lib/HDLRuby/backend/hruby_c_allocator.rb,
lib/HDLRuby/hruby_low_without_outread.rb,
lib/HDLRuby/hruby_low_without_parinseq.rb,
lib/HDLRuby/hruby_low_without_namespace.rb,
lib/HDLRuby/hruby_low_without_bit2vector.rb,
lib/HDLRuby/hruby_low_without_connection.rb,
lib/HDLRuby/hruby_low_without_subsignals.rb,
lib/HDLRuby/hruby_low_casts_without_expression.rb

Overview

Extends the SystemT class with functionality for breaking assingments to concats.

Direct Known Subclasses

High::SystemT

Constant Summary

Constants included from Low2Symbol

Low2Symbol::Low2SymbolPrefix, Low2Symbol::Low2SymbolTable, Low2Symbol::Symbol2LowTable

Instance Attribute Summary collapse

Attributes included from Hparent

#parent

Class Method Summary collapse

Instance Method Summary collapse

Methods included from ForceName

#extend_name!, #force_name!

Methods included from Low2Symbol

#to_sym

Methods included from Hparent

#absolute_ref, #hierarchy, #no_parent!

Constructor Details

#initialize(name, scope = nil) ⇒ SystemT

Creates a new system type named +name+ with +scope+. def initialize(name,scope)



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# File 'lib/HDLRuby/hruby_low.rb', line 122

def initialize(name,scope = nil)
    # Set the name as a symbol.
    @name = name.to_sym

    # Initialize the interface (signal instance lists).
    @inputs  = HashName.new # The input signals by name
    @outputs = HashName.new # The output signals by name
    @inouts  = HashName.new # The inout signals by name
    @interface = []         # The interface signals in order of
                            # declaration

#     self.set_scope(scope) if scope
# end

# # Set the scope of the systemT to +scope+.
# # Note: cannot override an existing scope.
# def set_scope(scope)
#     raise(AnyError,"Scope already present") if @scope
    # Check the scope
    unless scope.is_a?(Scope)
        raise AnyError,
              "Invalid class for a system instance: #{scope.class}"
    end
    # Set the parent of the scope
    scope.parent = self
    # Set the scope
    @scope = scope


    # The methods delegated to the scope.
    # Do not use Delegator to keep hand on the attributes of the class.

    [:add_scope,     :each_scope,                     # :delete_scope,
     :add_systemI,   :each_systemI,   :get_systemI,   # :delete_systemI,
     :add_inner,     :each_inner,     :get_inner,     # :delete_inner,
     :add_behavior,  :each_behavior,  :each_behavior_deep, # :delete_behavior,
     :add_connection,:each_connection,                # :delete_connection
    ].each do |meth_sym|
        define_singleton_method(meth_sym,
                                &(@scope.method(meth_sym).to_proc))
    end
end

Instance Attribute Details

#name ⇒ Object (readonly)

The name of the system.



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# File 'lib/HDLRuby/hruby_low.rb', line 115

def name
  @name
end

#scope ⇒ Object (readonly)

The scope of the system type.



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# File 'lib/HDLRuby/hruby_low.rb', line 118

def scope
  @scope
end

Class Method Details

.decompose_vec2d? ⇒ Boolean

Tell if 2d vector signals must be decomposed too.

Returns:

  • (Boolean) 


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# File 'lib/HDLRuby/hruby_low_without_subsignals.rb', line 36

def self.decompose_vec2d?
    @@decompose_vec2d
end

.get_indirect_verilog_regs(systemI, vname) ⇒ Object

Get signals indirectly refered that have to become reg in a sub system. +vname+ is the name of the system whose signals are to be processed.



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# File 'lib/HDLRuby/hruby_verilog.rb', line 2075

def self.get_indirect_verilog_regs(systemI,vname)
    # Get the sub systemT.
    sub_systemT = systemI.systemT
    # Get the indirect reg inside it.
    sub_systemT.each_behavior do |behavior|
        behavior.each_block_deep do |block|
            block.each_statement do |statement|
                if statement.is_a?(Transmit) &&
                        statement.left.to_verilog.include?(vname + ".")
                    puts "hierachical=#{statement.left.to_verilog}"
                    # HDLRuby::Low::VERILOG_REGS << SystemT.get_regs(statement.left.ref).to_verilog
                    HDLRuby::Low::VERILOG_REGS.concat( SystemT.get_regs(statement.left,vname).map(&:to_verilog))
                end
            end
        end
    end
    # And recurse on its systemIs.
    sub_systemT.each_systemI do |sub_systemI|
        SystemT.get_indirect_verilog_regs(sub_systemI,vname)
    end
end

.get_regs(expr, vname = nil) ⇒ Object

Get the signals that can be declared as reg. If +vname+ is given, use as base for reference name.



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# File 'lib/HDLRuby/hruby_verilog.rb', line 2053

def self.get_regs(expr,vname = nil)
    if expr.is_a?(RefConcat) then
        return expr.each_ref.map {|ref| self.get_regs(ref,vname) }.flatten
    elsif expr.is_a?(RefName) then
        if vname then
            puts "vname=#{vname} expr.name=#{expr.name}"
            if expr.ref && name_to_verilog(expr.name) == vname then
                return get_regs(expr.ref)
            else
                return []
            end
        else
            return [expr]
        end
    else
        return get_regs(expr.ref,vname)
    end
end

Instance Method Details

#add_inout(signal) ⇒ Object

Adds inout +signal+.



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# File 'lib/HDLRuby/hruby_low.rb', line 272

def add_inout(signal)
    # Check and add the signal.
    unless signal.is_a?(SignalI)
        raise AnyError,
              "Invalid class for a signal instance: #{signal.class}"
    end
    # if @inouts.include?(signal) then
    #     raise AnyError, "SignalI #{signal.name} already present."
    # end
    if @inouts.include?(signal) then
        signal.parent = self
        # Replace the signal.
        old_signal = @inouts[signal.name]
        @inouts.add(signal)
        @interface[@interface.index(old_signal)] = signal
    else
        # Set the parent of the signal.
        signal.parent = self
        # And add the signal.
        @inouts.add(signal)
        @interface << signal
    end
    return signal
end

#add_input(signal) ⇒ Object

Adds input +signal+.



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# File 'lib/HDLRuby/hruby_low.rb', line 219

def add_input(signal)
    # print "In #{self} add_input with signal: #{signal.name}\n"
    # Check and add the signal.
    unless signal.is_a?(SignalI)
        raise AnyError,
              "Invalid class for a signal instance: #{signal.class}"
    end
    # if @inputs.include?(signal) then
    #     raise AnyError, "SignalI #{signal.name} already present."
    # end
    if @inputs.include?(signal) then
        signal.parent = self
        # Replace the signal.
        old_signal = @inputs[signal.name]
        @inputs.add(signal)
        @interface[@interface.index(old_signal)] = signal
    else
        # Set the parent of the signal.
        signal.parent = self
        # And add the signal.
        @inputs.add(signal)
        @interface << signal
    end
    return signal
end

#add_output(signal) ⇒ Object

Adds output +signal+.



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# File 'lib/HDLRuby/hruby_low.rb', line 246

def add_output(signal)
    # Check and add the signal.
    unless signal.is_a?(SignalI)
        raise AnyError,
              "Invalid class for a signal instance: #{signal.class}"
    end
    # if @outputs.include?(signal) then
    #     raise AnyError, "SignalI #{signal.name} already present."
    # end
    if @outputs.include?(signal) then
        signal.parent = self
        # Replace the signal.
        old_signal = @outputs[signal.name]
        @outputs.add(signal)
        @interface[@interface.index(old_signal)] = signal
    else
        # Set the parent of the signal.
        signal.parent = self
        # And add the signal.
        @outputs.add(signal)
        @interface << signal
    end
    return signal
end

#bit2vector2inner! ⇒ Object

Replace bit to vector conversions by assignment to on bit of an intermediate inner vector.

NOTE: the result is the same systemT.



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# File 'lib/HDLRuby/hruby_low_without_bit2vector.rb', line 23

def bit2vector2inner!
    # puts "For system: #{self.name}"
    # First gather the bit conversions to vector.
    bits2vectors = Set.new
    gather_bits2vectors = proc do |node|
        if node.is_a?(Expression) && node.type == Bit &&
                node.parent.is_a?(Expression) && 
                # References are not relevant parents
                !node.parent.is_a?(Ref) && 
                # Neither do concat that are processed separatly
                !node.parent.is_a?(Concat) && 
                node.parent.type != Bit then
            # puts "node=#{node.to_high}, node.parent=#{node.parent}"
            bits2vectors.add(node)
        end
    end
    # Apply the procedure for gathering the read on outputs signals.
    self.scope.each_scope_deep do |scope|
        scope.each_connection do |connection|
            # Recurse on the connection.
            connection.each_node_deep(&gather_bits2vectors)
        end
        scope.each_behavior do |behavior|
            behavior.each_event do |event|
                gather_bits2vectors.(event.ref)
            end
            behavior.each_statement do |statement|
                # puts "statement=#{statement.class}"
                statement.each_node_deep(&gather_bits2vectors)
            end
        end
    end
    # puts "bits2vectors=#{bits2vectors.size}"

    # Create the 1-bit-vector type.
    vec1T = TypeVector.new(:"bit1",Bit,0..0)
    # Generate one inner 1-bit-vector signal per read output.
    bit2inner = {}
    bits2vectors.each do |node|
        # Generate the inner variable.
        sig = self.scope.add_inner(SignalI.new(HDLRuby::uniq_name,vec1T))
        ref = RefName.new(vec1T,RefThis.new,sig.name)
        bit2inner[node] = 
            [ ref, RefIndex.new(Bit,ref,Value.new(Integer,0)) ]
        # puts "new inner=#{out2inner[name].name}"
    end

    # Apply the replacement procedure on the code
    self.scope.each_scope_deep do |scope|
        scope.each_connection.to_a.each do |connection|
            connection.reassign_expressions!(bit2inner)
        end
        scope.each_behavior do |behavior|
            behavior.each_event do |event|
                event.reassign_expressions!(bit2inner)
            end
            behavior.block.reassign_expressions!(bit2inner)
        end
    end

    return self
end

#blocks2seq! ⇒ Object

Converts the par sub blocks to seq.



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# File 'lib/HDLRuby/hruby_low2seq.rb', line 21

def blocks2seq!
    # Recurse on the scope.
    self.scope.to_seq!
    return self
end

#boolean_in_assign2select! ⇒ Object

Converts booleans in assignments to select operators.



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# File 'lib/HDLRuby/hruby_low_bool2select.rb', line 22

def boolean_in_assign2select!
    self.scope.boolean_in_assign2select!
    return self
end

#break_concat_assigns! ⇒ Object

Breaks the assignments to concats.



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# File 'lib/HDLRuby/hruby_low_without_concat.rb', line 21

def break_concat_assigns!
    self.scope.break_concat_assigns!
end

#break_types! ⇒ Object

Breaks the hierarchical types into sequences of type definitions.



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# File 'lib/HDLRuby/hruby_low_without_namespace.rb', line 77

def break_types!
    self.scope.break_types!
end

#c_code_allocate(allocator) ⇒ Object

Allocates signals within C code using +allocator+.



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# File 'lib/HDLRuby/backend/hruby_c_allocator.rb', line 18

def c_code_allocate(allocator)
    self.scope.c_code_allocate(allocator)
end

#casts_without_expression! ⇒ Object

Extracts the expressions from the casts.



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# File 'lib/HDLRuby/hruby_low_casts_without_expression.rb', line 23

def casts_without_expression!
    self.scope.casts_without_expression!
    return self
end

#cleanup! ⇒ Object

Cleans up.



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# File 'lib/HDLRuby/hruby_low_cleanup.rb', line 22

def cleanup!
    # Gather the output and inout signals' names, they are used to
    # identify the signals that can be removed.
    keep = self.each_output.map {|sig| sig.name } +
           self.each_inout.map {|sig| sig.name }
    self.scope.cleanup!(keep)
end

#connections_to_behaviors! ⇒ Object

Remove the connections and replace them by behaviors. NOTE: one behavior is created for input connections and one for output ones while inout/inner-only connections are copied in both behaviors.



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# File 'lib/HDLRuby/hruby_low_without_connection.rb', line 25

def connections_to_behaviors!
    # Process the connections: create a behavior containing
    # them all within a par block.
    self.scope.each_scope_deep do |scope|
        if scope.each_connection.to_a.any? then
            inputs_blk = Block.new(:par)
            outputs_blk = Block.new(:par)
            # Timed block is not necessary anymore for initialization.
            # timed_blk = TimeBlock.new(:seq)
            timed_blk = Block.new(:seq)
            scope.each_connection do |connection|
                # puts "For connection: #{connection}"
                # Check the left and right of the connection
                # for input or output port.
                left = connection.left
                left_r = left.resolve
                # puts "left_r=#{left_r.name}" if left_r
                # puts "left_r.parent=#{left_r.parent.name}" if left_r && left_r.parent
                right = connection.right
                right_r = right.resolve if right.respond_to?(:resolve)
                # puts "right_r=#{right_r.name}" if right_r
                # puts "right_r.parent=#{right_r.parent.name}" if right_r && right_r.parent
                # if right.is_a?(Value) then
                if right.immutable? then
                    # Right is value, the new transmit is to add
                    # to the timed block.
                    timed_blk.add_statement(
                        Transmit.new(left.clone,right.clone))
                    # No more process for this connection.
                    next
                end

                # Check if left is an input or an output.
                left_is_i = left_is_o = false
                if left_r && left_r.parent.is_a?(SystemT) then
                    if left_r.parent.each_input.include?(left_r) then
                        # puts "Left is input."
                        # puts "Left is from systemI: #{left.from_systemI?}"
                        left_is_i = left.from_systemI?
                        left_is_o = !left_is_i
                    elsif left_r.parent.each_output.include?(left_r) then
                        # puts "Left is output."
                        # puts "Left is from systemI: #{left.from_systemI?}"
                        left_is_o = left.from_systemI?
                        left_is_i = !left_is_o
                    end
                end
                # Check if right is an input or an output.
                right_is_i = right_is_o = false
                if right_r && right_r.parent.is_a?(SystemT) then
                    if right_r.parent.each_input.include?(right_r) then
                        # puts "Right is input."
                        # puts "Right is from systemI: #{right.from_systemI?}"
                        right_is_i = right.from_systemI?
                        right_is_o = !right_is_i
                    elsif right_r.parent.each_output.include?(right_r) then
                        # puts "Right is output."
                        # puts "Right is from systemI: #{right.from_systemI?}"
                        right_is_o = right.from_systemI?
                        right_is_i = !right_is_o
                    end
                end
                # puts "left_is_i=#{left_is_i} left_is_o=#{left_is_o}"
                # puts "right_is_i=#{right_is_i} right_is_o=#{right_is_o}"
                # Fills the relevant block.
                if (left_is_i) then
                    inputs_blk.add_statement(
                        Transmit.new(left.clone,right.clone))
                elsif (right_is_i) then
                    inputs_blk.add_statement(
                        Transmit.new(right.clone,left.clone))
                elsif (left_is_o) then
                    # puts "left=#{left} right=#{right}"
                    outputs_blk.add_statement(
                        Transmit.new(right.clone,left.clone))
                elsif (right_is_o) then
                    outputs_blk.add_statement(
                        Transmit.new(left.clone,right.clone))
                else
                    # # puts "left/right is inout"
                    # if (left.is_a?(Ref)) then
                    #     inputs_blk.add_statement(
                    #         Transmit.new(left.clone,right.clone))
                    # end
                    # if (right.is_a?(Ref)) then
                    #     outputs_blk.add_statement(
                    #         Transmit.new(right.clone,left.clone))
                    # end
                    # Both or neither input/output, make a behavior
                    # for each.
                    if (left.is_a?(Ref) && 
                            !(left_r && left_r.immutable?)) then
                        blk = Block.new(:par)
                        blk.add_statement(
                            Transmit.new(left.clone,right.clone))
                        scope.add_behavior(Behavior.new(blk))
                    end
                    if (right.is_a?(Ref) &&
                            !(right_r && right_r.immutable?)) then
                        blk = Block.new(:par)
                        blk.add_statement(
                            Transmit.new(right.clone,left.clone))
                        scope.add_behavior(Behavior.new(blk))
                    end
                end
            end
            # Adds the behaviors.
            if inputs_blk.each_statement.any? then
                scope.add_behavior(Behavior.new(inputs_blk))
            end
            if outputs_blk.each_statement.any? then
                scope.add_behavior(Behavior.new(outputs_blk))
            end
            if timed_blk.each_statement.any? then
                # No more required to be timed.
                # scope.add_behavior(TimeBehavior.new(timed_blk))
                scope.add_behavior(Behavior.new(timed_blk))
            end
        end
    end
end

#delete_inout!(signal) ⇒ Object

Deletes an inout.



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# File 'lib/HDLRuby/hruby_low_mutable.rb', line 85

def delete_inout!(signal)
    if @inouts.key?(signal.name) then
        # The signal is present, delete it.
        @inouts.delete(signal.name)
        @interface.delete(signal)
        # And remove its parent.
        signal.parent = nil
    end
    signal
end

#delete_input!(signal) ⇒ Object

Deletes an input.



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# File 'lib/HDLRuby/hruby_low_mutable.rb', line 61

def delete_input!(signal)
    if @inputs.key?(signal.name) then
        # The signal is present, delete it.
        @inputs.delete(signal.name)
        @interface.delete(signal)
        # And remove its parent.
        signal.parent = nil
    end
    signal
end

#delete_output!(signal) ⇒ Object

Deletes an output.



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# File 'lib/HDLRuby/hruby_low_mutable.rb', line 73

def delete_output!(signal)
    if @outputs.key?(signal.name) then
        # The signal is present, delete it.
        @outputs.delete(signal.name)
        @interface.delete(signal)
        # And remove its parent.
        signal.parent = nil
    end
    signal
end

#each_deep(&ruby_block) ⇒ Object

Iterates over each object deeply.

Returns an enumerator if no ruby block is given.



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# File 'lib/HDLRuby/hruby_low.rb', line 477

def each_deep(&ruby_block)
    # No ruby block? Return an enumerator.
    return to_enum(:each_deep) unless ruby_block
    # A ruby block? First apply it to current.
    ruby_block.call(self)
    # Then apply on each signal.
    self.each_signal do |signal|
        signal.each_deep(&ruby_block)
    end
    # Then apply on each scope.
    self.each_scope do |scope|
        scope.each_deep(&ruby_block)
    end
end

#each_inout(&ruby_block) ⇒ Object

Iterates over the inout signals.

Returns an enumerator if no ruby block is given.



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# File 'lib/HDLRuby/hruby_low.rb', line 320

def each_inout(&ruby_block)
    # No ruby block? Return an enumerator.
    return to_enum(:each_inout) unless ruby_block
    # A ruby block? Apply it on each inout signal instance.
    @inouts.each(&ruby_block)
end

#each_input(&ruby_block) ⇒ Object

Iterates over the input signals.

Returns an enumerator if no ruby block is given.



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# File 'lib/HDLRuby/hruby_low.rb', line 300

def each_input(&ruby_block)
    # No ruby block? Return an enumerator.
    return to_enum(:each_input) unless ruby_block
    # A ruby block? Apply it on each input signal instance.
    @inputs.each(&ruby_block)
end

#each_output(&ruby_block) ⇒ Object

Iterates over the output signals.

Returns an enumerator if no ruby block is given.



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# File 'lib/HDLRuby/hruby_low.rb', line 310

def each_output(&ruby_block)
    # No ruby block? Return an enumerator.
    return to_enum(:each_output) unless ruby_block
    # A ruby block? Apply it on each output signal instance.
    @outputs.each(&ruby_block)
end

#each_signal(&ruby_block) ⇒ Object

Iterates over all the signals of the interface of the system.

Returns an enumerator if no ruby block is given.



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# File 'lib/HDLRuby/hruby_low.rb', line 331

def each_signal(&ruby_block)
    # No ruby block? Return an enumerator.
    return to_enum(:each_signal) unless ruby_block
    # A ruby block? Apply it on each signal instance.
    @interface.each(&ruby_block)
end

#each_signal_all(&ruby_block) ⇒ Object

Iterates over all the signals of the system including its scope (input, output, inout, inner).

Returns an enumerator if no ruby block is given.



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# File 'lib/HDLRuby/hruby_low.rb', line 342

def each_signal_all(&ruby_block)
    # No ruby block? Return an enumerator.
    return to_enum(:each_signal_all) unless ruby_block
    # A ruby block? Apply it on each signal instance.
    @inputs.each(&ruby_block)
    @outputs.each(&ruby_block)
    @inouts.each(&ruby_block)
    # And each signal of the direct scope.
    @scope.each_signal(&ruby_block)
end

#each_signal_deep(&ruby_block) ⇒ Object

Iterates over all the signals of the system type and its scope.



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# File 'lib/HDLRuby/hruby_low.rb', line 354

def each_signal_deep(&ruby_block)
    # No ruby block? Return an enumerator.
    return to_enum(:each_signal_deep) unless ruby_block
    # A ruby block?
    # First iterate over the current system type's signals.
    # self.each_signal_all(&ruby_block)
    self.each_signal(&ruby_block)
    # Then apply on the behaviors (since in HDLRuby:High, blocks can
    # include signals).
    @scope.each_signal_deep(&ruby_block)
end

#each_systemT_deep(&ruby_block) ⇒ Object

Iterates over the systemT deeply if any.

Returns an enumerator if no ruby block is given.



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# File 'lib/HDLRuby/hruby_low.rb', line 495

def each_systemT_deep(&ruby_block)
    # No ruby block? Return an enumerator.
    return to_enum(:each_systemT_deep) unless ruby_block
    # A ruby block? First apply it to current.
    ruby_block.call(self)
    # And recurse on the systemT accessible through the instances.
    self.scope.each_scope_deep do |scope|
        scope.each_systemI do |systemI|
            # systemI.systemT.each_systemT_deep(&ruby_block)
            systemI.each_systemT do |systemT|
                systemT.each_systemT_deep(&ruby_block)
            end
        end
    end
end

#each_systemT_deep_ref(&ruby_block) ⇒ Object

Iterates over the systemT deeply if any in order of reference to ensure the refered elements are processed first.

Returns an enumerator if no ruby block is given.



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# File 'lib/HDLRuby/hruby_low.rb', line 515

def each_systemT_deep_ref(&ruby_block)
    # No ruby block? Return an enumerator.
    return to_enum(:each_systemT_deep_ref) unless ruby_block
    # A ruby block? 
    # Recurse on the systemT accessible through the instances.
    self.scope.each_scope_deep do |scope|
        scope.each_systemI do |systemI|
            # systemI.systemT.each_systemT_deep(&ruby_block)
            systemI.each_systemT do |systemT|
                systemT.each_systemT_deep_ref(&ruby_block)
            end
        end
    end
    # Finally apply it to current.
    ruby_block.call(self)
end

#eql?(obj) ⇒ Boolean

Comparison for hash: structural comparison.

Returns:

  • (Boolean) 


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# File 'lib/HDLRuby/hruby_low.rb', line 169

def eql?(obj)
    return false unless obj.is_a?(SystemT)
    return false unless @name.eql?(obj.name)
    return false unless @scope.eql?(obj.scope)
    idx = 0
    obj.each_input do |input|
        return false unless @inputs[input.name].eql?(input)
        idx += 1
    end
    return false unless idx == @inputs.size
    idx = 0
    obj.each_output do |output|
        return false unless @outputs[output.name].eql?(output)
        idx += 1
    end
    return false unless idx == @outputs.size
    idx = 0
    obj.each_inout do |inout|
        return false unless @inouts[inout.name].eql?(inout)
        idx += 1
    end
    return false unless idx == @inouts.size
    return true
end

#explicit_types! ⇒ Object

Explicit the types conversions in the system.



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# File 'lib/HDLRuby/hruby_low_fix_types.rb', line 19

def explicit_types!
    # No direct fix required in the system, recurse on the scope.
    self.scope.explicit_types!
    return self
end

#extract_port_assign!(systemI, signal) ⇒ Object

Extracts the assignments to port +systemI.signal+ and returns the resulting reference to a port wire.

NOTE: assumes to_upper_space! and with_port! has been called.



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# File 'lib/HDLRuby/hruby_verilog.rb', line 2028

def extract_port_assign!(systemI,signal)
    # Extract the assignment.
    assign = nil
    self.each_connection.to_a.each do |connection|
        if self.port_assign?(connection.left,systemI,signal) then
            # The left is the port.
            # Delete the connection.
            self.scope.delete_connection!(connection)
            # And return a copy of the right.
            return connection.right.clone
        elsif self.port_assign?(connection.right,systemI,signal) then
            # The right is the port.
            # Delete the connection.
            self.scope.delete_connection!(connection)
            # And return a copy of the left.
            return connection.left.clone
        end
    end
    # No port found, nothing to do
    return nil
end

#get_all_inouts ⇒ Object

Gets an array containing all the inout signals.



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# File 'lib/HDLRuby/hruby_low.rb', line 398

def get_all_inouts
    return each_inout.to_a
end

#get_all_inputs ⇒ Object

Gets an array containing all the input signals.



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# File 'lib/HDLRuby/hruby_low.rb', line 388

def get_all_inputs
    return each_input.to_a
end

#get_all_outputs ⇒ Object

Gets an array containing all the output signals.



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# File 'lib/HDLRuby/hruby_low.rb', line 393

def get_all_outputs
    return each_output.to_a
end

#get_all_signals ⇒ Object

Gets an array containing all the signals.



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# File 'lib/HDLRuby/hruby_low.rb', line 403

def get_all_signals
    return each_signal.to_a
end

#get_by_name(name) ⇒ Object

Find an inner object by +name+. NOTE: return nil if not found.



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# File 'lib/HDLRuby/hruby_low_resolve.rb', line 21

def get_by_name(name)
    # Ensure the name is a symbol.
    name = name.to_sym
    # Look in the interface.
    found = self.get_signal(name)
    return found if found
    # Maybe it is the scope.
    return self.scope if self.scope.name == name
    # Look in the scope.
    return self.scope.get_by_name(name)
end

#get_inout(name) ⇒ Object

Gets an inout signal by +name+.



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# File 'lib/HDLRuby/hruby_low.rb', line 418

def get_inout(name)
    return @inouts[name.to_sym]
end

#get_input(name) ⇒ Object

Gets an input signal by +name+.



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# File 'lib/HDLRuby/hruby_low.rb', line 408

def get_input(name)
    return @inputs[name.to_sym]
end

#get_interface(i) ⇒ Object

Gets an interface signal by order of declaration +i+.



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# File 'lib/HDLRuby/hruby_low.rb', line 434

def get_interface(i)
    return @interface[i]
end

#get_output(name) ⇒ Object

Gets an output signal by +name+.



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# File 'lib/HDLRuby/hruby_low.rb', line 413

def get_output(name)
    return @outputs[name.to_sym]
end

#get_signal(name) ⇒ Object

Gets a signal by +name+.



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# File 'lib/HDLRuby/hruby_low.rb', line 428

def get_signal(name)
    return get_input(name) || get_output(name) || get_inout(name) # ||
           # get_inner(name)
end

#has_inout? ⇒ Boolean

Tells if there is any output signal.

Returns:

  • (Boolean) 


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# File 'lib/HDLRuby/hruby_low.rb', line 377

def has_inout?
    return !@inouts.empty?
end

#has_input? ⇒ Boolean

Tells if there is any input signal.

Returns:

  • (Boolean) 


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# File 'lib/HDLRuby/hruby_low.rb', line 367

def has_input?
    return !@inputs.empty?
end

#has_output? ⇒ Boolean

Tells if there is any output signal.

Returns:

  • (Boolean) 


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# File 'lib/HDLRuby/hruby_low.rb', line 372

def has_output?
    return !@outputs.empty?
end

#has_signal? ⇒ Boolean

Tells if there is any signal (including in the scope of the system).

Returns:

  • (Boolean) 


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# File 'lib/HDLRuby/hruby_low.rb', line 382

def has_signal?
    return ( self.has_input? or self.has_output? or self.has_inout? or
             self.has_inner? )
end

#hash ⇒ Object

Hash function.



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# File 'lib/HDLRuby/hruby_low.rb', line 195

def hash
    return [@name,@scope,@inputs,@outputs,@inouts].hash
end

#initial_concat_to_timed! ⇒ Object

Converts initial concat of values of signals to assignment in timed blocks (for making the code compatible with verilog translation).

NOTE: Assumes such array as at the top level.



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# File 'lib/HDLRuby/hruby_low_without_concat.rb', line 30

def initial_concat_to_timed!
    self.scope.initial_concat_to_timed!
end

#map_inouts!(&ruby_block) ⇒ Object

Maps on the inouts.



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# File 'lib/HDLRuby/hruby_low_mutable.rb', line 52

def map_inouts!(&ruby_block)
    @inouts.map! do |inout|
        inout = ruby_block.call(inout)
        inout.parent = self unless inout.parent
        inout
    end
end

#map_inputs!(&ruby_block) ⇒ Object

Maps on the inputs.



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# File 'lib/HDLRuby/hruby_low_mutable.rb', line 34

def map_inputs!(&ruby_block)
    @inputs.map! do |input|
        input = ruby_block.call(input)
        input.parent = self unless input.parent
        input
    end
end

#map_outputs!(&ruby_block) ⇒ Object

Maps on the outputs.



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# File 'lib/HDLRuby/hruby_low_mutable.rb', line 43

def map_outputs!(&ruby_block)
    @outputs.map! do |output|
        output = ruby_block.call(output)
        output.parent = self unless output.parent
        output
    end
end

#mixblocks2seq! ⇒ Object

Converts the par sub blocks to seq if they are not full par.



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# File 'lib/HDLRuby/hruby_low2seq.rb', line 28

def mixblocks2seq!
    # Recurse on the scope.
    self.scope.mixblocks2seq!
end

#outread2inner! ⇒ Object

Replace read of output signal to read of intermediate inner signal.

NOTE: the result is the same systemT.



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# File 'lib/HDLRuby/hruby_low_without_outread.rb', line 23

def outread2inner!
    # puts "For system: #{self.name}"
    # First gather the read on output signals.
    outreads = {}
    gather_outreads = proc do |node|
        # puts "node=#{node.name}" if node.is_a?(RefName)
        if node.is_a?(RefName) && !node.leftvalue? then
            name = node.name
            # puts "name=#{name}"
            sig = self.get_output(name)
            outreads[node.name] = node if sig
        end
    end
    # Apply the procedure for gathering the read on outputs signals.
    self.scope.each_scope_deep do |scope|
        scope.each_connection do |connection|
            connection.each_node_deep(&gather_outreads)
        end
        scope.each_behavior do |behavior|
            behavior.each_event do |event|
                gather_outreads.(event.ref)
            end
            behavior.each_statement do |statement|
                # puts "statement=#{statement.class}"
                statement.each_node_deep(&gather_outreads)
            end
        end
    end
    # puts "outreads=#{outreads.keys}"

    # Generate one inner signal per read output.
    out2inner = {}
    outreads.each do |name,node|
        # Generate the inner variable.
        out2inner[name] = 
         self.scope.add_inner(SignalI.new(HDLRuby::uniq_name,node.type))
        # puts "new inner=#{out2inner[name].name}"
    end

    # Replace the output by the corresponding inner in the
    # expressions.
    replace_name = proc do |node| # The replacement procedure.
        # Only single name reference are to be replaced, the others
        # cannot correspond to output signal.
        if node.is_a?(RefName) && node.ref.is_a?(RefThis) &&
                !node.parent.is_a?(RefName) then
            inner = out2inner[node.name]
            # puts "node=#{node.name} inner=#{inner}"
            # puts "Replace name: #{node.name} by #{inner.name}" if inner
            node.set_name!(inner.name) if inner
        end
    end
    # Apply the replacement procedure on the code
    self.scope.each_scope_deep do |scope|
        scope.each_connection do |connection|
            connection.each_node_deep do |node|
                replace_name.(node)
            end
        end
        scope.each_behavior do |behavior|
            behavior.each_event do |event|
                event.ref.each_node_deep do |node|
                    replace_name.(node)
                end
            end
            behavior.each_statement do |statement|
                statement.each_node_deep do |node|
                    replace_name.(node)
                end
            end
        end
    end

    # Finally connect the inner to the output.
    out2inner.each do |out,inner|
        self.scope.add_connection(
         Connection.new(RefName.new(inner.type,RefThis.new,out),
                        RefName.new(inner.type,RefThis.new,inner.name)))
    end

    return self
end

#par_in_seq2seq! ⇒ Object

Converts par blocks within seq blocks to seq blocks.



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# File 'lib/HDLRuby/hruby_low_without_parinseq.rb', line 21

def par_in_seq2seq!
    self.scope.par_in_seq2seq!
end

#port_assign?(expr, systemI, signal) ⇒ Boolean

Tells if an expression is a reference to port +systemI.signal+.

Returns:

  • (Boolean) 


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# File 'lib/HDLRuby/hruby_verilog.rb', line 2019

def port_assign?(expr, systemI, signal)
    return expr.is_a?(RefName) && expr.name == signal.name &&
        expr.ref.is_a?(RefName) && expr.ref.name == systemI.name
end

#port_output_connection?(connection) ⇒ Boolean

Tells if a connection is actually a port connection.

Returns:

  • (Boolean) 


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# File 'lib/HDLRuby/hruby_verilog.rb', line 2005

def port_output_connection?(connection)
    return self.each_systemI.find do |systemI|
        if connection.right.is_a?(RefName) && 
                connection.right.ref.is_a?(RefName) &&
                systemI.name == connection.right.ref.name
            puts "port_connection for right=#{connection.right.name} and systemI=#{systemI.name}"
            true
        else
            false
        end
    end
end

#replace_names!(former, nname) ⇒ Object

Replaces recursively +former+ name by +nname+ until it is redeclared.



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# File 'lib/HDLRuby/hruby_low_without_namespace.rb', line 63

def replace_names!(former,nname)
    # Replace owns name if required.
    if self.name == former then
        self.set_name!(nname)
    end
    # Recurse on the interface.
    self.each_input {|input| input.replace_names!(former,nname) }
    self.each_output {|output| output.replace_names!(former,nname) }
    self.each_inout {|inout| inout.replace_names!(former,nname) }
    # Recurse on the scope.
    self.scope.replace_names!(former,nname)
end

#select2case! ⇒ Object

Converts the Select expressions to Case statements.



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# File 'lib/HDLRuby/hruby_low_without_select.rb', line 60

def select2case!
    self.scope.select2case!
end

#set_name!(name) ⇒ Object

Sets the +name+.



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# File 'lib/HDLRuby/hruby_low_mutable.rb', line 20

def set_name!(name)
    @name = name.to_sym
end

#set_scope!(scope) ⇒ Object

Sets the +scope+.



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# File 'lib/HDLRuby/hruby_low_mutable.rb', line 25

def set_scope!(scope)
    unless scope.is_a?(Scope) then
        raise AnyError, "Invalid class for a scope: #{scope.class}"
    end
    scope.parent = self
    @scope = scope
end

#signal2subs!(decompose_vec2d = false) ⇒ Object

Decompose the hierarchical signals in the statements. If +decompose_vec2d+ is true then also decompose 2 dimension vectors (e.g., for Verilog HDL that does not support handling such signals as usual expressions).



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# File 'lib/HDLRuby/hruby_low_without_subsignals.rb', line 30

def signal2subs!(decompose_vec2d = false)
    @@decompose_vec2d = decompose_vec2d == true
    self.scope.signal2subs!
end

#to_c(res, level = 0, *hnames) ⇒ Object

Generates the text of the equivalent HDLRuby code. +level+ is the hierachical level of the object and +hnames+ is the list of extra h files to include. def to_c(level = 0, *hnames)



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# File 'lib/HDLRuby/hruby_low2c.rb', line 175

def to_c(res, level = 0, *hnames)
    # puts "SystemT.to_c with name=#{Low2C.obj_name(self)}#{@wrapper ? " and wrapper=#{Low2C.obj_name(@wrapper)}" : ""}"
    # The header
    # res = Low2C.includes(*hnames)
    res << Low2C.includes(*hnames)

    # Declare the global variable holding the system.
    res << "SystemT " << Low2C.obj_name(self) << ";\n\n"

    # Generate the signals of the system.
    # self.each_signal { |signal| signal.to_c(level) }
    if ((defined? @wrapper) && @wrapper) then
        # It is a reconfiguring system, alias the signals.
        wrap_signals = @wrapper.each_signal.to_a
        self.each_signal.with_index do |signal,i|
            signal.to_c_alias(res,wrap_signals[i],level)
        end
    else
        # It is a single system, default generation.
        self.each_signal { |signal| signal.to_c(res,level) }
    end

    # Generate the code for all the blocks included in the system.
    self.scope.each_scope_deep do |scope|
        scope.each_behavior do |behavior|
            # res << behavior.block.to_c_code(level)
            behavior.block.to_c_code(res,level)
        end
    end

    # Generate the code for all the values included in the system.
    self.each_signal do |signal|
        # res << signal.value.to_c_make(level) if signal.value
        signal.value.each_node_deep do |node|
            # res << node.to_c_make(level) if node.respond_to?(:to_c_make)
            node.to_c_make(res,level) if node.respond_to?(:to_c_make)
        end if signal.value
    end
    self.scope.each_scope_deep do |scope|
        scope.each_inner do |signal|
            signal.value.each_node_deep do |node|
                # res << node.to_c_make(level) if node.respond_to?(:to_c_make)
                node.to_c_make(res,level) if node.respond_to?(:to_c_make)
            end if signal.value
        end
    end
    self.scope.each_block_deep do |block|
    # puts "treating for block=#{Low2C.obj_name(block)} with=#{block.each_inner.count} inners"
        block.each_inner do |signal|
            signal.value.each_node_deep do |node|
                # res << node.to_c_make(level) if node.respond_to?(:to_c_make)
                node.to_c_make(res,level) if node.respond_to?(:to_c_make)
            end if signal.value
        end
    end
    self.scope.each_node_deep do |node|
        # res << node.to_c_make(level) if node.is_a?(Value)
        node.to_c_make(res,level) if node.is_a?(Value)
    end

    # Generate the scope.
    # res << self.scope.to_c(level)
    self.scope.to_c(res,level)

    # Generate the entity
    res << "SystemT " << Low2C.make_name(self) << "() {\n"
    # Creates the structure.
    res << " " * (level+1)*3
    res << "SystemT systemT = malloc(sizeof(SystemTS));\n"
    res << " " * (level+1)*3
    res << "systemT->kind = SYSTEMT;\n";

    # Sets the global variable of the system.
    res << "\n"
    res << " " * (level+1)*3
    res << Low2C.obj_name(self) << " = systemT;\n"

    # Set the owner if any.
    if @owner then
        res << " " * (level+1)*3
        res << "systemT->owner = (Object)"
        res << Low2C.obj_name(@owner) << ";\n"
    else
        res << "systemT->owner = NULL;\n"
    end

    # The name
    res << " " * (level+1)*3
    res << "systemT->name = \"#{self.name}\";\n"

    # The ports
    # Inputs
    res << " " * (level+1)*3
    res << "systemT->num_inputs = #{self.each_input.to_a.size};\n"
    res << " " * (level+1)*3
    res << "systemT->inputs = calloc(sizeof(SignalI),"
    res << "systemT->num_inputs);\n"
    self.each_input.with_index do |input,i|
        res << " " * (level+1)*3
        res << "systemT->inputs[#{i}] = "
        res << Low2C.make_name(input) << "();\n"
    end
    # Outputs
    res << " " * (level+1)*3
    res << "systemT->num_outputs = #{self.each_output.to_a.size};\n"
    res << " " * (level+1)*3
    res << "systemT->outputs = calloc(sizeof(SignalI),"
    res << "systemT->num_outputs);\n"
    self.each_output.with_index do |output,i|
        res << " " * (level+1)*3
        res << "systemT->outputs[#{i}] = "
        res << Low2C.make_name(output) << "();\n"
    end
    # Inouts
    res << " " * (level+1)*3
    res << "systemT->num_inouts = #{self.each_inout.to_a.size};\n"
    res << " " * (level+1)*3
    res << "systemT->inouts = calloc(sizeof(SignalI)," +
           "systemT->num_inouts);\n"
    self.each_inout.with_index do |inout,i|
        res << " " * (level+1)*3
        res << "systemT->inouts[#{i}] = "
        res << Low2C.make_name(inout) << "();\n"
    end

    # Adds the scope.
    res << "\n"
    res << " " * (level+1)*3
    res << "systemT->scope = " << Low2C.make_name(self.scope) << "();\n"

    # Generate the Returns of the result.
    res << "\n"
    res << " " * (level+1)*3
    res << "return systemT;\n"
    # End of the system.
    res << " " * level*3
    res << "}"
    # Return the result.
    return res
end

#to_c_code(res, level) ⇒ Object

Generates the code for an execution starting from the system. +level+ is the hierachical level of the object. def to_c_code(level)



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# File 'lib/HDLRuby/hruby_low2c.rb', line 320

def to_c_code(res,level)
    res << " " * (level*3)
    res << Low2C.code_name(self) << "() {\n"
    # res << "printf(\"Executing #{Low2C.code_name(self)}...\\n\");"
    # Launch the execution of all the time behaviors of the
    # system.
    self.each_behavior_deep do |behavior|
        if behavior.is_a?(HDLRuby::Low::TimeBehavior) then
            res << " " * (level+1)*3
            res << Low2C.code_name(behavior.block) << "();\n"
        end
    end
    # Close the execution procedure.
    res << " " * level*3
    res << "}\n"
    # Return the result.
    return res
end

#to_ch(res) ⇒ Object

Generates the content of the h file. def to_ch



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# File 'lib/HDLRuby/hruby_low2c.rb', line 342

def to_ch(res)
    # res = ""
    # Declare the global variable holding the signal.
    res << "extern SystemT " << Low2C.obj_name(self) << ";\n\n"

    # Generate the access to the function making the systemT. */
    res << "extern SystemT " << Low2C.make_name(self) << "();\n\n"

    # Generate the accesses to the values.
    self.each_signal do |signal|
        # res << signal.value.to_ch if signal.value
        if signal.value then
            signal.value.each_node_deep do |node|
                # res << node.to_ch if node.is_a?(Value)
                node.to_ch(res) if node.is_a?(Value)
            end
        end
    end
    self.scope.each_scope_deep do |scope|
        scope.each_inner do |signal|
            if signal.value then
                signal.value.each_node_deep do |node|
                    # res << node.to_ch if node.is_a?(Value)
                    node.to_ch(res) if node.is_a?(Value)
                end
            end
        end
    end
    self.scope.each_block_deep do |block|
        block.each_inner do |signal|
            # signal.value.to_ch(res) if signal.value
            if signal.value then
                signal.value.each_node_deep do |node|
                    # res << node.to_ch if node.is_a?(Value)
                    node.to_ch(res) if node.is_a?(Value)
                end
            end
        end
        block.each_node_deep do |node|
            # res << node.to_ch if node.is_a?(Value)
            node.to_ch(res) if node.is_a?(Value)
        end
    end

    # Generate the accesses to the ports.
    # self.each_input  { |input|  res << input.to_ch }
    self.each_input  { |input|  input.to_ch(res) }
    # self.each_output { |output| res << output.to_ch }
    self.each_output { |output| output.to_ch(res) }
    # self.each_inout  { |inout|  res << inout.to_ch }
    self.each_inout  { |inout|  inout.to_ch(res) }

    # Generate the accesses to the scope.
    # res << self.scope.to_ch << "\n"
    self.scope.to_ch(res)
    res << "\n"

    return res;
end

#to_global_systemTs! ⇒ Object

Moves local systemTs to global.

NOTE: assumes to_upper_space! has been called.



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# File 'lib/HDLRuby/hruby_low_without_namespace.rb', line 45

def to_global_systemTs!
    # Force a name if not.
    self.force_name!
    # puts "to_global_systemTs! for #{self.name}"
    # For each local systemT
    self.scope.each_systemT.to_a.each do |systemT|
        # puts "Processing system: #{systemT}"
        # Rename it for globalization.
        former = systemT.name
        self.extend_name!(systemT)
        # Apply the renaming to all the inner objects.
        self.scope.replace_names_subs!(former,systemT.name)
        # Remove it.
        self.scope.delete_systemT!(systemT)
    end
end

#to_hdr(level = 0) ⇒ Object

Generates the text of the equivalent hdr text. +level+ is the hierachical level of the object.



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# File 'lib/HDLRuby/hruby_low2hdr.rb', line 64

def to_hdr(level = 0)
    # The resulting string.
    res = ""
    # Generate the header.
    res << " " * (level*3)
    res << "system :#{Low2HDR.hdr_decl_name(self.name)} do\n"
    # Generate the interface.
    # Inputs.
    self.each_input do |input|
        res << " " * ((level+1)*3)
        res << input.type.to_hdr(level+1) 
        res << ".input :" << Low2HDR.hdr_decl_name(input.name)
        res << "\n"
    end
    # Outputs.
    self.each_output do |output|
        res << " " * ((level+1)*3)
        res << output.type.to_hdr(level+1) 
        res << ".output :" << Low2HDR.hdr_decl_name(output.name)
        res << "\n"
    end
    # Inouts.
    self.each_inout do |inout|
        res << " " * ((level+1)*3)
        res << inout.type.to_hdr(level+1) 
        res << ".inout :" << Low2HDR.hdr_decl_name(inout.name)
        res << "\n"
    end
    # Generate the scope.
    res << " " * (level*3)
    res << "\n"
    res << self.scope.to_hdr(level+1,false)
    # End of the system.
    res << " " * (level*3)
    res << "end\n\n"
    # Return the result.
    return res
end

#to_high ⇒ Object

Creates a new high system type named +name+ with +scope+.



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# File 'lib/HDLRuby/hruby_low2high.rb', line 18

def to_high
    # Create the high system type.
    res = HDLRuby::High::SystemT.new(self.name,self.scope.to_high)
    # Add the inputs.
    self.each_input  { |i|  res.add_input(i.to_high) }
    # Add the outputs.
    self.each_output { |o|  res.add_output(o.to_high) }
    # Add the inouts.
    self.each_inout  { |io| res.add_inout(io.to_high) }
    return res
end

#to_upper_space! ⇒ Object

Moves the declarations to the upper namespace.



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# File 'lib/HDLRuby/hruby_low_without_namespace.rb', line 38

def to_upper_space!
    self.scope.to_upper_space!
end

#to_verilog(vcd = false) ⇒ Object

Converts the system to Verilog code. NOTE: if +vcd+ is true, generate verilog code whose simulation produces a vcd file.



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# File 'lib/HDLRuby/hruby_verilog.rb', line 2101

def to_verilog(vcd = false)
    # Create the name of the module.
    vname = name_to_verilog(self.name)
    # puts "Processing systemT named=#{vname}"
    # Detect the registers
    HDLRuby::Low::VERILOG_REGS.clear
    # The left values.
    self.each_behavior do |behavior|
        behavior.each_block_deep do |block|
            block.each_statement do |statement|
                if statement.is_a?(Transmit)
                    # HDLRuby::Low::VERILOG_REGS << SystemT.get_regs(statement.left).to_verilog
                    HDLRuby::Low::VERILOG_REGS.concat(SystemT.get_regs(statement.left).map(&:to_verilog))
                end
            end
        end
    end
    self.each_systemI do |systemI|
        SystemT.get_indirect_verilog_regs(systemI,vname)
    end
    # And the initialized signals.
    self.each_output do |output|
        # regs << output.to_verilog if output.value
        HDLRuby::Low::VERILOG_REGS << output.to_verilog if output.value
    end
    self.each_inner do |inner|
        # regs << inner.to_verilog if inner.value
        HDLRuby::Low::VERILOG_REGS << inner.to_verilog if inner.value
    end
    # Actual NOT...
    # # And the array types signals.
    # self.each_signal do |sig|
    #     if sig.type.vector? && sig.type.base.vector? then
    #         HDLRuby::Low::VERILOG_REGS << sig.to_verilog
    #     end
    # end
    # self.each_inner do |sig|
    #     if sig.type.vector? && sig.type.base.vector? then
    #         HDLRuby::Low::VERILOG_REGS << sig.to_verilog
    #     end
    # end

    # Code generation
    inputs = 0
    outputs = 0
    inout = 0

    inputs = self.each_input.to_a
    outputs = self.each_output.to_a
    inout = self.each_inout.to_a

    # Spelling necessary for simulation.
    code = "`timescale 1ps/1ps\n\n"

    # self.properties[:verilog_name] = vname
    # Output the module name.
    code << "module #{vname}("

    # Output the last two to the input. 
    inputs[0..-2].each do |input|
        code << " #{input.to_verilog},"
    end
    # When only input is used, it is necessary to close (), so it branches with if.
    if outputs.empty? && inout.empty? then
        if (inputs.empty?)
            code << " ); \n"
        end
    else
        code << " #{inputs.last.to_verilog}," unless inputs.empty?
    end

    # Output the last two to the output. 
    outputs[0..-2].each do |output|
        code << " #{output.to_verilog},"
    end
    # When only input and output are used, it is necessary to close (), so it branches with if.
    if inout.empty? then
        code << " #{outputs.last.to_verilog} ); \n" unless outputs.empty?
    else
        code << " #{outputs.last.to_verilog}," unless outputs.empty?
    end

    # Output the last two to the inout. 
    inout[0..-2].each do |inout|
        code << " #{inout.to_verilog},"
    end
    # There is no comma as it is the last one
    code << " #{inout.last.to_verilog} ); \n" unless inout.empty?

    # Declare "input"
    self.each_input do |input|
        if input.type.respond_to? (:each_type) then
            $vector_reg = "#{input.to_verilog}"
            $vector_cnt = 0
            input.type.each_type do |type|
                code << "input #{type.to_verilog} #{$vector_reg}:#{$vector_cnt};\n"
                $vector_cnt += 1
            end        
        else
            code << "   input#{input.type.to_verilog} #{input.to_verilog};\n"
        end
    end

    # Declare "output"
    self.each_output do |output|
        if output.type.respond_to? (:each_type) then
            $vector_reg = "#{output.to_verilog}"
            $vector_cnt = 0
            output.type.each_type do |type|
                # if regs.include?(type.name) then
                if HDLRuby::Low::VERILOG_REGS.include?(type.name) then
                    code << "   output reg"
                else
                    code << "   output"
                end
                code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt}"
                if output.value then
                    # There is an initial value.
                    code << " = #{output.value.to_verilog}"
                end
                code << ";\n"
                $vector_cnt += 1
            end        
        else
            if HDLRuby::Low::VERILOG_REGS.include?(output.to_verilog) then
                code << "   output reg"
            else
                code << "   output"
            end
            code << "#{output.type.to_verilog} #{output.to_verilog}"
            if output.value then
                # There is an initial value.
                code << " = #{output.value.to_verilog}"
            end
            code << ";\n"
        end
    end

    # Declare "inout"
    self.each_inout do |inout|
        if inout.type.respond_to? (:each_type) then
            $vector_reg = "#{inout.to_verilog}"
            $vector_cnt = 0
            inout.type.each_type do |type|
                code << "inout #{type.to_verilog} #{$vector_reg}:#{$vector_cnt};\n"
                $vector_cnt += 1
            end        
        else
            code << "   inout#{inout.type.to_verilog} #{inout.to_verilog};\n"
        end
    end

    # Generate content code.
    codeC = ""

    # Arrays to initialize.
    arrays_to_init = []

    # Declare "inner".
    self.each_inner do |inner|
        if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
            codeC << "   reg"
        else
            codeC << "   wire"
        end

        if inner.type.base? 
            if inner.type.base.base? 
                codeC << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
            else
                codeC << "#{inner.type.to_verilog} #{inner.to_verilog}"
            end
        else
            codeC << " #{inner.type.to_verilog}#{inner.to_verilog}"
        end
        if inner.value then
            val = inner.value
            val = val.child while val.is_a?(Cast)
            if val.is_a?(Concat) then
                arrays_to_init << [inner,val]
            else
                # There is an initial value.
                codeC << " = #{inner.value.to_verilog}"
            end
        end
        codeC << ";\n"
    end

    # If there is scope in scope, translate it.
    self.each_scope do |scope|
        scope.each_inner do |inner|
            if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
                codeC << "   reg "
            else
                codeC << "   wire "
            end

            if inner.type.respond_to? (:base) 
                if inner.type.base.base?
                    codeC << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
                else
                    codeC << "#{inner.type.to_verilog} #{inner.to_verilog}"
                end
            else
                codeC << "inner #{inner.type.to_verilog} #{inner.to_verilog}"
            end
            if inner.value then
                # There is an initial value.
                codeC << " = #{inner.value.to_verilog}"
            end
            codeC << ";\n"
        end    

        scope.each_connection do |connection|
            codeC << "\n" 
            codeC << "#{connection.to_verilog}"
        end
    end

    codeC << "\n"

    # puts "For system=#{self.name}"
    # transliation of the instantiation part.
    # Generate the instances connections.
    self.each_systemI do |systemI| 
        # puts "Processing systemI = #{systemI.name}"
        # Its Declaration.
        codeC << " " * 3
        systemT = systemI.systemT
        codeC << name_to_verilog(systemT.name) << " "
        vname = name_to_verilog(systemI.name)
        # systemI.properties[:verilog_name] = vname
        codeC << vname << "("
        # Its ports connections
        # Inputs
        systemT.each_input do |input|
            ref = self.extract_port_assign!(systemI,input)
            if ref then
                codeC << "." << name_to_verilog(input.name) << "(" 
                codeC << ref.to_verilog
                codeC << "),"
            end
        end
        # Outputs
        systemT.each_output do |output|
            ref = self.extract_port_assign!(systemI,output)
            if ref then
                codeC << "." << name_to_verilog(output.name) << "(" 
                codeC << ref.to_verilog
                codeC << "),"
            end
        end
        # Inouts
        systemT.each_inout do |inout|
            ref = self.extract_port_assign!(systemI,inout)
            if ref then
                codeC << "." << name_to_verilog(inout.name) << "(" 
                codeC << ref.to_verilog
                codeC << "),"
            end
        end
        # Remove the last "," if any for conforming with Verilog syntax.
        codeC.chop! if codeC[-1] == ","
        # And close the port connection.
        codeC << ");\n"
    end



    # translation of the connection part (assigen).
    self.each_connection do |connection|
        codeC << "#{connection.to_verilog}\n"
    end

    # Translation of behavior part (always).
    $timebeh_shown = false
    self.each_behavior do |behavior|
        timebeh = false
        if behavior.block.is_a?(TimeBlock) then
            # Tell it is a time behavior for further processing.
            timebeh = true
            # Deprecated with new TimeRepeat.
            #
            # # Extract and translate the TimeRepeat separately.
            # behavior.each_block_deep do |blk|
            #     codeC << blk.repeat_to_verilog!
            # end
            # And generate an initial block.
            codeC << "   initial "
        else
            # Generate a standard process.
            codeC << "\n   always @( "
            # If there is no "always" condition, it is always @("*").
            if behavior.each_event.to_a.empty? then
                codeC << "*"
            else
                event = behavior.each_event.to_a
                event[0..-2].each do |event|
                    # If "posedge" or "negedge" does not exist, the variable is set to condition.
                    if (event.type.to_s != "posedge" && event.type.to_s != "negedge") then
                        codeC << "#{event.ref.to_verilog}, "
                    else
                        # Otherwise, it outputs "psoedge" or "negedge" as a condition.
                        codeC << "#{event.type.to_s} #{event.ref.to_verilog}, "
                    end
                end
                # Since no comma is necessary at the end, we try not to separate commas separately at the end.
                if (event.last.type.to_s != "posedge" && event.last.type.to_s != "negedge") then
                    codeC << "#{event.last.ref.to_verilog}"
                else
                    codeC << "#{event.last.type.to_s} #{event.last.ref.to_verilog}"
                end
            end
            codeC << " ) "
        end

        if vcd && timebeh && !$timebeh_shown then
            codeC << behavior.block.to_verilog(3,name_to_verilog(self.name))
            $timebeh_shown = true
        else
            codeC << behavior.block.to_verilog
        end

    end

    # Generate the code for the initialization of the arrays.
    if arrays_to_init.any? then
        codeC << "   initial begin\n"
        arrays_to_init.each do |(sig,val)|
            val.each_expression.with_index do |expr,i|
                # Initialization, therefore maybe no cast required...
                # if sig.value.is_a?(Cast) then
                #     expr = Cast.new(sig.value.type,expr.clone)
                # end
                codeC << "      ";
                codeC << "#{sig.to_verilog}[#{i}]=#{expr.to_verilog};\n"
            end
        end
        codeC << "   end\n"
    end

    # Conclusion.
    codeC << "\nendmodule"

    # Adds the truncing functions.
    code << TruncersI.dump
    # Adds the indexing functions.
    code << IndexersI.dump
    # Adds the content code.
    code << codeC
    return code
end

#to_vhdl(level = 0) ⇒ Object

Generates the text of the equivalent HDLRuby::High code. +level+ is the hierachical level of the object.



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# File 'lib/HDLRuby/hruby_low2vhd.rb', line 348

def to_vhdl(level = 0)
    # The resulting string.
    res = ""
    # Generate the entity
    # The header
    res << Low2VHDL.packages(" " * (level*3))
    res << " " * (level*3)
    res << "entity #{Low2VHDL.entity_name(self.name)} is\n"
    # The ports
    if self.each_input.any? || self.each_output.any? ||
           self.each_inout.any? then
        res << " " * ((level+1)*3)
        res << "port (\n"
        # Inputs
        self.each_input do |input|
            res << " " * ((level+2)*3)
            res << Low2VHDL.vhdl_name(input.name) << ": in " 
            res << input.type.to_vhdl << ";\n"
        end
        # Outputs
        self.each_output do |output|
            res << " " * ((level+2)*3)
            res << Low2VHDL.vhdl_name(output.name) << ": out " 
            res << output.type.to_vhdl << ";\n"
        end
        # Inouts
        self.each_inout do |inout|
            res << " " * ((level+2)*3)
            res << Low2VHDL.vhdl_name(inout.name) << ": inout " 
            res << inout.type.to_vhdl << ";\n"
        end
        # Remove the last ";" for conforming with VHDL syntax.
        res[-2..-1] = "\n" if res[-2] == ";"
        res << " " * ((level+1)*3)
        # Close the port declaration.
        res << ");\n"
    end
    # Close the entity
    res << " " * (level*3)
    res << "end #{Low2VHDL.entity_name(self.name)};\n\n"


    # Generate the architecture.
    res << " " * (level*3)
    res << "architecture #{Low2VHDL.architecture_name(self.name)} "
    res << "of #{Low2VHDL.entity_name(self.name)} is\n"
    # Generate the scope.
    res << "\n"
    res << self.scope.to_vhdl(level+1)
    # End of the system.
    res << " " * (level*3)
    res << "end #{Low2VHDL.architecture_name(self.name)};\n\n"
    # Return the result.
    return res
end

#to_viz ⇒ Object 



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# File 'lib/HDLRuby/hruby_viz.rb', line 4350

def to_viz
  puts "Generating VIZ representation for system #{self.name}..."
  # The registers.
  regs = {}
  # The existing ports by name for further connections.
  ports = Hash.new { |h,k| h[k] = [] }
  # The ports explicit connections lists.
  # Named +links+ to avoid confusion with HDLRuby connection objects.
  links = []
  # Create the viz for the current systemT.
  world = HDLRuby::Viz::IC.new(self.name.to_s,:module)
  # Adds its ports.
  self.each_input  do |port|
    puts "Adding input port #{port.name} to #{world.name}"
    name = port.name.to_s
    ports[name] << world.add_port(name, :input)
  end
  self.each_output do |port|
    puts "Adding output port #{port.name} to #{world.name}"
    name = port.name.to_s
    ports[name] << world.add_port(name, :output)
  end
  self.each_inout  do |port| 
    puts "Adding inout port #{port.name} to #{world.name}"
    name = port.name.to_s
    ports[name] << world.add_port(name, :inout)
  end
  # Recurse on the scope.
  self.scope.to_viz(world,regs,ports,links)
  # Do the connection by maching names of each port and handling
  # the connections between signals.
  # First connect the ports with same name of different ic.
  # ports.each_value do |subs|
  ports.each do |name,subs|
    # Skip connection to registers, they are processed later.
    next if regs[name]
    # Not a register, can go on.
    subs.each do |p0|
      subs.each do |p1|
        # puts "p0=#{p0.name} ic=#{p0.ic.name} p1=#{p1.name} ic=#{p1.ic.name}"
        if p0.ic != p1.ic then
          # Ports are from different IC, we can connect thems.
          puts "Connect by name in ic=#{world.name}."
          world.connect(p0,p1) unless p0.targets.include?(p1)
        end
      end
    end
  end
  # Connect the registers.
  ports.each do |name,subs|
    # Check if there is a register corresponding to the port
    # (full port or sub port of the register).
    next if name.include?("$") # Skip register ports which are targets.
    rname = name
    while !regs.key?(rname) do
      break unless rname.include?(".")
      rname = rname.gsub(/\.[^.]*$/,"")
    end
    reg = regs[rname]
    next unless reg
    # Connect the register, once per ic and direction.
    subs.uniq {|p| [p.ic,p.direction] }.each do |p|
      # puts "Connect to register port name #{name} in ic=#{world.name} with port=#{p.name}"
      if p.direction == :output then
        world.connect(p,ports[HDLRuby::Viz.reg2input_name(name)][0])
      elsif p.direction == :input then
        world.connect(ports[HDLRuby::Viz.reg2output_name(name)][0],p)
      else
        world.connect(p,ports[HDLRuby::Viz.reg2input_name(name)][0])
        world.connect(ports[HDLRuby::Viz.reg2output_name(name)][0],p)
      end
    end
  end
  # Then connects according to the explicit connections.
  links.each do |n0,n1|
    puts "n0=#{n0} n1=#{n1}"
    # Is n0 a register?
    reg = regs[n0]
    if reg then
      # Yes, connect its input port.
      p0 = ports[HDLRuby::Viz.reg2input_name(n0)][0]
    else
      # No, it is a normal port.
      p0 = ports[n0][0]
    end
    # In n1 a register?
    reg = regs[n1]
    if reg then
      # Yes, connect its output port.
      p1 = ports[HDLRuby::Viz.reg2output_name(n1)][0]
    else
      # No, it is a normal port.
      p1 = ports[n1][0]
    end
    # NOTE: p0 or p1 may be empty if outside current module.
    world.connect(p0,p1) unless (!p0 or !p1 or p0.targets.include?(p1))
  end
  # Remove the dangling input ports in registers (they are ROMS).
  regs.each_value do |reg|
    to_remove_input = reg.ports.select {|p| p.direction==:input }.all? do
      |p|
      p.targets.none?
    end
    if to_remove_input then
      reg.ports.delete_if {|p| p.direction == :input }
    end
  end
  # Return the resulting visualization.
  return world
end

#with_boolean! ⇒ Object

Converts to a variable-compatible system.

NOTE: the result is the same systemT.



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# File 'lib/HDLRuby/hruby_low_with_bool.rb', line 64

def with_boolean!
    self.scope.each_scope_deep do |scope|
        scope.each_connection { |connection| connection.with_boolean! }
        scope.each_behavior   { |behavior|   behavior.with_boolean! }
    end
    return self
end

#with_port! ⇒ Object

Converts to a port-compatible system.

NOTE: the result is the same systemT.



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# File 'lib/HDLRuby/hruby_low_with_port.rb', line 29

def with_port!
    self.scope.with_port!
    return self
end

#with_var! ⇒ Object

Converts to a variable-compatible system.

NOTE: the result is the same systemT.



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# File 'lib/HDLRuby/hruby_low_with_var.rb', line 25

def with_var!
    self.each_behavior { |behavior| behavior.with_var! }
    return self
end

#wrapper ⇒ Object

Gets the configuration wrapper if any.



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# File 'lib/HDLRuby/hruby_low.rb', line 203

def wrapper
    return defined? @wrapper ? @wrapper : nil
end

#wrapper=(systemT) ⇒ Object

Sets the configuration wrapper to +systemT+.



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# File 'lib/HDLRuby/hruby_low.rb', line 208

def wrapper=(systemT)
    unless systemT.is_a?(SystemT) then
        raise "Invalid class for a wrapper system type: #{systemT}."
    end
    @wrapper = systemT
end