Class: ClassHDL::ImplicitPortBase

Inherits:
Object
  • Object
show all
Defined in:
lib/tdl/class_hdl/hdl_module_def.rb

Instance Attribute Summary collapse

Instance Method Summary collapse

Constructor Details

#initialize(sdlm, args = {}) ⇒ ImplicitPortBase

Returns a new instance of ImplicitPortBase.



153
154
155
156
157
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 153

def initialize(sdlm,args={})
    @chain = []
    @sdlm = sdlm
    @up_args = args
end

Dynamic Method Handling

This class handles dynamic methods through the method_missing method

#method_missing(method, *args, &block) ⇒ Object



231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 231

def method_missing(method,*args,&block)
    ## 检查是否有用户定义的类型数据
    if @sdlm.respond_to?(method)
        if @sdlm.send(method).is_a?(EnumStruct)
            self.speciel_type = @sdlm.send(method).typedef_name
            self.sub_type = @sdlm.send(method)  ## 针对struct 内元素
            self
        elsif @sdlm.send(method).is_a?(StructMeta)
            self.speciel_type = @sdlm.send(method).name
            self.sub_type = @sdlm.send(method) ## 针对struct 内元素
            self
        else 
            ## 判断 是否是头部引入的包
            ##  input.<package_name> 返回自身calss
            # if method.to_s.eql? @sdlm.head_import_package.to_s
            if @sdlm.head_import_packages.map{ |e| e.to_s }.include?(method.to_s )
                package_name = method.to_s
                return ImplicitPortBasePackage.new(self,package_name)
            else 
                ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
                    args = args[0] || {}
                    @up_args = @up_args.merge(args)
                    self.-(method)
                end
            end
        end
    else 
        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
            args = args[0] || {}
            @up_args = @up_args.merge(args)
            self.-(method)
        end
    end
end

Instance Attribute Details

#_struct_qObject

Returns the value of attribute _struct_q.



152
153
154
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 152

def _struct_q
  @_struct_q
end

#chainObject

Returns the value of attribute chain.



152
153
154
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 152

def chain
  @chain
end

#sdlmObject

Returns the value of attribute sdlm.



152
153
154
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 152

def sdlm
  @sdlm
end

#speciel_typeObject

Returns the value of attribute speciel_type.



152
153
154
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 152

def speciel_type
  @speciel_type
end

#sub_typeObject

Returns the value of attribute sub_type.



152
153
154
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 152

def sub_type
  @sub_type
end

Instance Method Details

#-(name) ⇒ Object



173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 173

def - (name)
    if name !~ /\w+/
        raise TDLError.new("PORT #{name} Illegle ")
    end

    if name.is_a? StringBandItegration
        raise TDLError.new("简化定义模式不允许传入 StringBandItegration 类型")
    end

    args = @up_args
    # @sdlm.Input(method,dsize:args[:dsize] || 1,dimension:args[:dimension]||[],pin:args[:pin]||[],iostd:args[:iostd]||[],pin_prop:args[:pin_prop])
    if $_implicit_curr_itgt_.slast
        name = name.to_inp($_implicit_curr_itgt_.last)
    end

    ## >>>>当使用 chain 定义时忽略 args dimension<<<
    ## 修改成当为struct时 需要不同处理方式
    
    if @chain.any? 
        unless @_struct_q
            args[:dsize] = @chain.last
            if @chain[1]
                args[:dimension] = @chain[0,@chain.size-1]
            end
        else 
            args[:dimension] = @chain
        end
    end

    sdlm_port(name,args)
end

#[](*a) ⇒ Object



266
267
268
269
270
271
272
273
274
275
276
277
278
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 266

def [](*a)
    if a.empty?
        raise TdlError.new("参数不能为空")
    end
    # @chain ||= []
    new_dla = self.class.new(@sdlm,@up_args)
    new_dla.chain = @chain + a
    ## 继承
    new_dla._struct_q = _struct_q
    new_dla.speciel_type = speciel_type
    new_dla.sub_type = sub_type
    new_dla
end

#add_struct_method(obj) ⇒ Object



280
281
282
283
284
285
286
287
288
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 280

def add_struct_method(obj)
    if sub_type.is_a? StructMeta
        @sub_type.struct_slots.each do |e|
            obj.define_singleton_method(e.name) do 
                TdlSpace::ArrayChain.new("#{obj.name}.#{e.name}".to_nq)
            end
        end
    end
end

#clock(*args) ⇒ Object



205
206
207
208
209
210
211
212
213
214
215
216
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 205

def clock(*args)
    if args.any?
        if args[0].is_a? Hash 
            @clock_freqM = args[0][:freqM]
        else 
            @clock_freqM = args[0]
        end 
    else  
        @clock_freqM = nil
    end
    return self
end

#logicObject



163
164
165
166
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 163

def logic 
    @speciel_type = 'logic'
    return self
end

#reset(*args) ⇒ Object



218
219
220
221
222
223
224
225
226
227
228
229
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 218

def reset(*args)
    if args.any?
        if args[0].is_a? Hash 
            @reset_active = args[0][:active]
        else 
            @reset_active = args[0]
        end 
    else  
        @reset_active = nil
    end
    return self
end

#sdlm_port(method = nil, args = {}) ⇒ Object



159
160
161
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 159

def sdlm_port(method=nil,args={})
    raise TDLError.new "ImplicitPortBase slot <#{method}>"
end

#wireObject



168
169
170
171
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 168

def wire 
    @speciel_type = 'wire'
    return self 
end