Module: TdlSpace::VarElemenAttr
- Included in:
- TdlBaseInterface
- Defined in:
- lib/tdl/rebuild_ele/ele_base.rb
Instance Method Summary collapse
- #_io_map(tdl_key, hdl_key, default_value, flag, other = nil) ⇒ Object
- #clock_io_map(tdl_key, hdl_key, default_freqM = nil) ⇒ Object
- #comm_io_map(tdl_key, hdl_key, default_value = nil) ⇒ Object
- #comm_io_maps_same(*tdl_keys) ⇒ Object
-
#gen_sv_interface(path) ⇒ Object
生成 SV 文件.
-
#get_class_var(name, default = nil) ⇒ Object
hdl_name :axi_stream_inf modports :master,:slaver,:mirror,:mirror_out param_map :dsize,‘DSIZE’,8 ## <tdl_key><hdl_key><default_value> clock_io_map :aclk,:aclk,100 ## <tdl_key><hdl_key><default_freqM> reset_io_map :aresetn,:aresetn sdata_maps :axis_tvalid,:axis_tready,:axis_tuser pdata_map :axis_tdata, pdata_map :axis_tkeep,[] pdata_map :axis_tcnt.
- #hdl_name(name, *nicknames) ⇒ Object
- #modports(*args) ⇒ Object
- #param_map(tdl_key, hdl_key, default_value = nil) ⇒ Object
- #pdata_map(name, dimension = []) ⇒ Object
- #reset_io_map(tdl_key, hdl_key, active = 'low') ⇒ Object
- #sdata_maps(*args) ⇒ Object
- #set_class_var(name, value) ⇒ Object
Instance Method Details
#_io_map(tdl_key, hdl_key, default_value, flag, other = nil) ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 194 def _io_map(tdl_key,hdl_key,default_value,flag,other=nil) interface_io = get_class_var('origin_interface_io',{}) interface_io[tdl_key.to_s] = [hdl_key.to_s,default_value,flag,other] set_class_var('origin_interface_io',interface_io) ## 定义实例方法 self.class_exec(tdl_key) do |tdl_key| define_method(tdl_key) do rel = self.instance_variable_get("@_#{tdl_key}_") || default_value rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module) end define_method("#{tdl_key}=") do |arg| self.instance_variable_set("@_#{tdl_key}_",arg) end end end |
#clock_io_map(tdl_key, hdl_key, default_freqM = nil) ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 148 def clock_io_map(tdl_key,hdl_key,default_freqM=nil) _io_map(tdl_key,hdl_key,nil,"clock",default_freqM) ## 定义实例方法 self.class_exec(tdl_key) do |tdl_key| define_method('clock') do rel = self.instance_variable_get("@_#{tdl_key}_") if !dimension || dimension.empty? rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module) else rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}[0].#{hdl_key}", belong_to_module: belong_to_module) end end define_method("clock=") do |arg| self.instance_variable_set("@_#{tdl_key}_",arg) end end end |
#comm_io_map(tdl_key, hdl_key, default_value = nil) ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 184 def comm_io_map(tdl_key,hdl_key,default_value=nil) _io_map(tdl_key,hdl_key,default_value,nil) end |
#comm_io_maps_same(*tdl_keys) ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 188 def comm_io_maps_same(*tdl_keys) tdl_keys.each do |e| comm_io_map(e,e,nil) end end |
#gen_sv_interface(path) ⇒ Object
生成 SV 文件
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 235 def gen_sv_interface(path) File.open(File.join(path,get_class_var('hdl_name')+".sv"),'w') do |f| inerface_params = get_class_var('origin_interface_params',{}) par_str = [] inerface_params.each do |k,v| par_str << " parameter #{v[0]} = #{v[1]}" end interface_io = get_class_var('origin_interface_io',{}) clock_reset_str = [] sdata_str = [] pdata_str = [] interface_io.each do |k,v| ## 查找clock reset if v[2]=="clock" || v[2]=="reset" clock_reset_str << " input #{v[0]}" end ## 单信号 if v[2] == "sdata" sdata_str << "logic #{v[0]};" end ## 多信号 if v[2] == "pdata" dv = v[3] dv.map! do |e| if inerface_params.keys.include?(e.to_s ) inerface_params[e.to_s][0] else e.to_s end end dv_str = dv.map do |e| "[#{e}-1:0]" end.join() pdata_str << "logic #{dv_str} #{v[0]};" end end if par_str.any? par_str = "#(\n#{par_str.join(",\n")}\n)" else par_str = '' end if clock_reset_str.any? clock_reset_str = "\n"+clock_reset_str.join(",\n")+"\n" else clock_reset_str = '' end if sdata_str.any? sdata_str = "\n"+sdata_str.join("\n")+"\n" else sdata_str = "" end if pdata_str.any? pdata_str = "\n"+pdata_str.join("\n")+"\n" else pdata_str = '' end interface_modports = get_class_var('interface_modports',[]) sub_modport = [] interface_modports.each do |e| interface_modport_signals_in = get_class_var("#{e}_interface_modport_signals_input",[]) interface_modport_signals_out = get_class_var("#{e}_interface_modport_signals_output",[]) sub_modport << "modport #{e} (\n" xsub_modport = [] xsub_modport += interface_modport_signals_in.map do |m| if inerface_params.keys.include?(m.to_s ) inerface_params[m.to_s][0] else m.to_s end end.map do |m| "input #{m}" end xsub_modport += interface_modport_signals_out.map do |m| if inerface_params.keys.include?(m.to_s ) inerface_params[m.to_s][0] else m.to_s end end.map do |m| "output #{m}" end sub_modport << xsub_modport.join(",\n") sub_modport << "\n);\n" end if sub_modport.any? sub_modport = sub_modport.join('') else sub_modport = '' end f.puts "interface #{get_class_var('hdl_name')} #{par_str} (#{clock_reset_str});#{sdata_str}#{pdata_str}" f.puts sub_modport f.puts "endinterface:#{get_class_var('hdl_name')}" end end |
#get_class_var(name, default = nil) ⇒ Object
hdl_name :axi_stream_inf modports :master,:slaver,:mirror,:mirror_out param_map :dsize,‘DSIZE’,8 ## <tdl_key><hdl_key><default_value> clock_io_map :aclk,:aclk,100 ## <tdl_key><hdl_key><default_freqM> reset_io_map :aresetn,:aresetn sdata_maps :axis_tvalid,:axis_tready,:axis_tuser
pdata_map :axis_tdata,[:dsize]
pdata_map :axis_tkeep,[]
pdata_map :axis_tcnt
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 20 def get_class_var(name,default=nil) # begin # instance_variable_get("@_#{name}_") # rescue # instance_variable_set("@_#{name}_",nil) # end unless instance_variable_get("@_#{name}_") instance_variable_set("@_#{name}_",default) container = instance_variable_get("@_#{name}_") else container = instance_variable_get("@_#{name}_") end return container end |
#hdl_name(name, *nicknames) ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 43 def hdl_name(name,*nicknames) # @@__hdl_name__ = name.to_s set_class_var('hdl_name',name.to_s) ## 给 sdlmodule 定义例化方法 ## 例化名 ## 比如 sv 接口 axi4,可以在tdl里面这样用 axi4() ; `name`=axi4 self.class_exec(name) do |name| SdlModule.class_exec(name,self) do |name,ele_class| define_method(name) do |args={}| hash = args || {} hash[:belong_to_module] = self rel = TdlSpace::DefEleBaseArrayChain.new(hash) rel.tclass = ele_class return rel end nicknames.each do |nn| alias_method nn,name end end _self = self TdlSpace::DefPortArrayChain.class_exec(name,self) do |name,ele_class| define_method(name) do rel = TdlSpace::DefPortEleBaseArrayChain.new(ele_class,belong_to_module) return rel end nicknames.each do |nn| alias_method nn,name end end end ## 给例化模块时的 SdlInstPortSugar 添加 方法 SdlInstPortSugar.class_exec(name,nicknames) do |name,nicknames| define_method(name) do return self end nicknames.each do |ne| define_method(ne) do return self end end end end |
#modports(*args) ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 94 def modports(*args) # @@__interface_modports__ ||= [] # @@__interface_modports__ += args interface_modports = get_class_var('interface_modports',[]) interface_modports += args set_class_var('interface_modports',interface_modports) args.each do |e| # puts ("modport_#{e}_input") define_singleton_method("modport_#{e}_input") do |*xargs| interface_modport_signals = get_class_var("#{e}_interface_modport_signals_input",[]) interface_modport_signals += xargs interface_modport_signals.uniq! set_class_var("#{e}_interface_modport_signals_input",interface_modport_signals) end define_singleton_method("modport_#{e}_output") do |*xargs| interface_modport_signals = get_class_var("#{e}_interface_modport_signals_output",[]) interface_modport_signals += xargs interface_modport_signals.uniq! set_class_var("#{e}_interface_modport_signals_output",interface_modport_signals) end end end |
#param_map(tdl_key, hdl_key, default_value = nil) ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 121 def param_map(tdl_key,hdl_key,default_value=nil) interface_params = get_class_var('origin_interface_params',{}) interface_params[tdl_key.to_s] = [hdl_key.to_s,default_value] set_class_var('origin_interface_params',interface_params) ## 定义实例方法 self.class_exec(tdl_key,hdl_key) do |tdl_key,hdl_key| define_method(tdl_key) do rel = self.instance_variable_get("@_#{tdl_key}_") unless rel TdlSpace::ArrayChain.create(obj: "#{inst_name}.#{hdl_key}".to_nq, belong_to_module: belong_to_module) else rel end end define_method("#{tdl_key}=") do |arg| self.instance_variable_set("@_#{tdl_key}_",arg) end define_method(hdl_key) do self.send(tdl_key) end end end |
#pdata_map(name, dimension = []) ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 224 def pdata_map(name,dimension=[]) _io_map(name,name,nil,'pdata',dimension) self.class_exec(name) do |e| define_method(e) do TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{e}", belong_to_module: belong_to_module) end end end |
#reset_io_map(tdl_key, hdl_key, active = 'low') ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 168 def reset_io_map(tdl_key,hdl_key,active='low') _io_map(tdl_key,hdl_key,nil,"reset",active.to_s.downcase) ## 定义实例方法 self.class_exec(tdl_key) do |tdl_key| define_method('reset') do rel = self.instance_variable_get("@_#{tdl_key}_") rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module) end define_method("reset=") do |arg| self.instance_variable_set("@_#{tdl_key}_",arg) end end end |
#sdata_maps(*args) ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 213 def sdata_maps(*args) args.each do |e| _io_map(e,e,nil,'sdata',nil) self.class_exec(e) do |e| define_method(e) do TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{e}", belong_to_module: belong_to_module) end end end end |
#set_class_var(name, value) ⇒ Object
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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 37 def set_class_var(name,value) # rel = get_class_var(name) instance_variable_set("@_#{name}_",value) container = instance_variable_get("@_#{name}_") end |