Class: TestUnitModule

Inherits:
SdlModule show all
Defined in:
lib/tdl/sdlmodule/test_unit_module.rb

Overview

TestUnitModule 是在编译完 TopModule TB后才会运行

Instance Attribute Summary

Attributes inherited from SdlModule

#create_tcl, #dont_gen_sv, #ex_down_code, #ex_param, #ex_port, #ex_up_code, #head_import_packages, #instance_and_children_module, #instanced_and_parent_module, #module_name, #origin_sv, #out_sv_path, #path, #real_sv_path, #target_class, #techbench

Class Method Summary collapse

Instance Method Summary collapse

Methods inherited from SdlModule

#<<, #>>, #Always, #AlwaysComb, #Always_comb, #Always_ff, #Assign, #CASE, #CASEX, #Clock, #CommonCFGReg, #DEFAULT, #Def, #ELSE, #ELSIF, #FOR, #FOREACH, #IF, #Initial, #Inout, #Input, #Instance, #Itgt_Instance, Main, #NameSpaceAdd, #Output, #Parameter, #Parameters, #Reset, #StateMachine, #TrackInf, #TryDef, #WHEN, #__contain_hdl__, #__ref_children_modules__, #add_children_modules, #add_parent_modules, #add_to_dve_wave, #add_to_new_module, #all_ref_sdlmodules, allmodule_name, #always_ff, #always_sim, #assert, #assert_error, #assert_format_error, #assert_old, base_hdl_ref, #bits, #build_module, #build_module_verb, #call_instance, call_module, #children_inst_tree, #clog2, #contain_hdl, #debugLogic, #def_struct, #define_ele, echo_tracked_by_dve, #enum, exist_module?, #function, gen_dev_wave_tcl, #gen_dev_wave_tcl, gen_sv_module, #gen_sv_module, #generate, #genvar, #has_inward_inst?, #has_signal?, #implicit_inst_module_method_missing, #initial, #initial_exec, #inout, #input, #instance_draw, #instanced, #inward_inst, #localparam, #logic, #logic_bind_, #macro_add_vcs, #macro_def, #method_missing, #negedge, #output, #parameter, #parents_inst_tree, #path_refs, #port, #posedge, #pretty_ref_hdl_moduls_echo, #ref_modules, #require_hdl, #require_package, #root_ref, #rubyOP, #same_clock_domain, #show_ports, #signal, #top_module_ref?, #top_tb_ref?, #track_signals_hash, #tracked_by_dve, tracked_by_dve, #try_call_ele, #urandom_range, #var_common, #vars_define_inst, #vars_exec_inst, #vcs_string, #verify

Constructor Details

#initialize(name: "tdlmodule", out_sv_path: nil) ⇒ TestUnitModule

Returns a new instance of TestUnitModule.



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# File 'lib/tdl/sdlmodule/test_unit_module.rb', line 208

def initialize(name: "tdlmodule",out_sv_path: nil)
    super(name: name,out_sv_path: out_sv_path)
    # @dve_wave_signals = []
end

Dynamic Method Handling

This class handles dynamic methods through the method_missing method in the class SdlModule

Class Method Details

.be_instanced_by_sim ⇒ Object 



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# File 'lib/tdl/sdlmodule/test_unit_module.rb', line 239

def self.be_instanced_by_sim
    @@__be_instanced_by_sim__ || []
end

.echo_be_instanced_by_sim ⇒ Object 



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# File 'lib/tdl/sdlmodule/test_unit_module.rb', line 243

def self.echo_be_instanced_by_sim
    @@__be_instanced_by_sim__ ||= []

    _module_name = []
    _ref_module_name = []
    _signal_name = []
    _ref_module_path = []

    _max_module_name = 'test_module'.size 
    _max_signal_name = 'SIGNAL'.size 
    _max_ref = 'REF_MODULE'.size
    @@__be_instanced_by_sim__.each do |tm|
        __root_ref_eles__ = tm.root_ref_eles

        __root_ref_eles__.each do |ele|
            _module_name << tm.module_name
            _ref_module_name << ele.belong_to_module.module_name
            _signal_name << ele.to_s 
            _ref_module_path << File.expand_path(ele.belong_to_module.real_sv_path)

            if tm.module_name.size > _max_module_name
                _max_module_name    = tm.module_name.size 
            end 

            if ele.belong_to_module.module_name.size > _max_ref
                _max_ref  = ele.belong_to_module.module_name.size 
            end 

            if ele.to_s.size > _max_signal_name
                _max_signal_name = ele.to_s.size 
            end
        end
    end

    collect = ["[%5s]    %-#{_max_module_name}s    %#{_max_ref}s  %-#{_max_signal_name}s    %s" % ['index', 'TEST-MODULE','REF-MODULE','SIGNAL', 'REF-MODULE-PATH'] ] 

    _module_name.each_index do |index|
        collect << "[%5d]    %-#{_max_module_name}s    %#{_max_ref}s  %-#{_max_signal_name}s    %s" % [index+1, _module_name[index], _ref_module_name[index], _signal_name[index], _ref_module_path[index]]
    end

    collect.join("\n")
end

.gen_dve_tcl(filepath) ⇒ Object 



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# File 'lib/tdl/sdlmodule/test_unit_module.rb', line 287

def self.gen_dve_tcl(filepath)


end

Instance Method Details

#add_root_ref_ele(*eles) ⇒ Object 



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# File 'lib/tdl/sdlmodule/test_unit_module.rb', line 224

def add_root_ref_ele(*eles)
    @__root_ref_eles__ ||= []
    @__root_ref_eles__ += eles
    @__root_ref_eles__.uniq!
end

#be_instanced_by_sim ⇒ Object 



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# File 'lib/tdl/sdlmodule/test_unit_module.rb', line 234

def be_instanced_by_sim
    @@__be_instanced_by_sim__ ||= []
    @@__be_instanced_by_sim__ << self
end

#root_ref_eles ⇒ Object 



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# File 'lib/tdl/sdlmodule/test_unit_module.rb', line 230

def root_ref_eles 
    @__root_ref_eles__ || []
end

#test_unit_init(&block) ⇒ Object 



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# File 'lib/tdl/sdlmodule/test_unit_module.rb', line 213

def test_unit_init(&block)
    Initial do 
        to_down_pass    <= 1.b0
        initial_exec("wait(from_up_pass)")
        initial_exec("$root.#{TopModule.current.techbench.module_name}.test_unit_region = \"#{module_name}\"")
        initial_exec("$display(\"--------------- Current test_unit <%0s> --------------------\", \"#{module_name}\")")
        block.call ## collect __root_ref_eles__ at here
        to_down_pass    <= 1.b1
    end
end