Class: Logic

Inherits:
SignalElm show all
Includes:
BaseModule, ClassHDL::AssignDefOpertor, ClassHDL::RandomNum
Defined in:
lib/tdl/elements/logic.rb,
lib/tdl/elements/logic.rb,
lib/tdl/Logic/logic_edge.rb,
lib/tdl/Logic/logic_main.rb,
lib/tdl/exlib/logic_verify.rb,
lib/tdl/Logic/logic_latency.rb,
lib/tdl/class_hdl/hdl_random.rb,
lib/tdl/bfm/logic_initial_block.rb,
lib/tdl/class_hdl/hdl_redefine_opertor.rb

Overview

EDGE METHOD

Direct Known Subclasses

DebugLogic

Constant Summary collapse

INPUT = 
"INPUT"
OUTPUT = 
"OUTPUT"
INOUT = 
"INOUT"
Synth_REP =

parse text for autogen method and constant ###

/\(\*\s+logic\s*=\s*"true"\s+\*\)/i
OP_SYMBOLS = 
%w{+ - * / % > < >= <= << | &}

Instance Attribute Summary collapse

Attributes inherited from BaseElm

#belong_to_module

Class Method Summary collapse

Instance Method Summary collapse

Methods included from ClassHDL::AssignDefOpertor

curr_assign_block, curr_assign_block=, curr_assign_block_stack, curr_opertor_stack, included, init_op_methods, use_new_yield_opertors, use_old_cond_opertors, with_new_assign_block, with_new_opertor, with_normal_opertor, with_rollback_opertors

Methods included from ClassHDL::RandomNum

#precent_false, #precent_true

Methods included from BaseModule

#length

Methods inherited from SignalElm

inherited, subclass

Methods inherited from BaseElm

#matrix, #name_copy, #path_refs, recfg_nc, #s

Methods included from TdlSpace::ExCreateTP

#root_ref

Methods included from AxiTdl::TestUnitTrack

#tracked_by_dve

Constructor Details

#initialize(name: "tmp", dsize: 1, port: false, default: nil, msb_high: true, dimension: [], type: "logic", belong_to_module: nil) ⇒ Logic

Returns a new instance of Logic.



24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
 
# File 'lib/tdl/elements/logic.rb', line 24

def initialize(name:"tmp",dsize:1,port: false,default: nil,msb_high: true,dimension: [],type: "logic",belong_to_module: nil)
    @name   = name
    # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Logic.id
    @dsize = dsize
    @port = port
    @default = default
    # @msb_high = msb_high
    @dimension = dimension
    @type = type
    # raise TdlError.new("#{name} DATA ERROR")  unless dsize.is_a? Fixnum
    # raise TdlError.new("STOP")  if @id == 10
    name_legal?(name)
    if block_given?
        yield
    end

    @belong_to_module = belong_to_module

    unless @belong_to_module
        raise TdlError.new("Logic<#{@name}> be not belong_to_module")
    end

end

Instance Attribute Details

#clock ⇒ Object

@@logic_expression = [] @@logic_expression_def = [] @@logic_expression_record = []

@@condition_expression = []



14
15
16
 
# File 'lib/tdl/Logic/logic_main.rb', line 14

def clock
  @clock
end

#dimension ⇒ Object (readonly)

Returns the value of attribute dimension.



23
24
25
 
# File 'lib/tdl/elements/logic.rb', line 23

def dimension
  @dimension
end

#dsize ⇒ Object

attr_reader :dsize



22
23
24
 
# File 'lib/tdl/elements/logic.rb', line 22

def dsize
  @dsize
end

#ghost ⇒ Object

attr_reader :dsize



22
23
24
 
# File 'lib/tdl/elements/logic.rb', line 22

def ghost
  @ghost
end

#id ⇒ Object

attr_reader :dsize



22
23
24
 
# File 'lib/tdl/elements/logic.rb', line 22

def id
  @id
end

#name ⇒ Object

attr_reader :dsize



22
23
24
 
# File 'lib/tdl/elements/logic.rb', line 22

def name
  @name
end

#port ⇒ Object (readonly)

Returns the value of attribute port.



23
24
25
 
# File 'lib/tdl/elements/logic.rb', line 23

def port
  @port
end

#reset ⇒ Object

@@logic_expression = [] @@logic_expression_def = [] @@logic_expression_record = []

@@condition_expression = []



14
15
16
 
# File 'lib/tdl/Logic/logic_main.rb', line 14

def reset
  @reset
end

#type ⇒ Object

attr_reader :dsize



22
23
24
 
# File 'lib/tdl/elements/logic.rb', line 22

def type
  @type
end

Class Method Details

.exp_element(b) ⇒ Object 



165
166
167
168
169
170
171
 
# File 'lib/tdl/Logic/logic_main.rb', line 165

def self.exp_element(b)
    if b.is_a? Proc
        b.call
    else
        b.to_s
    end
end

.parse_ports(port_str) ⇒ Object 



286
287
288
289
290
 
# File 'lib/tdl/elements/logic.rb', line 286

def self.parse_ports(port_str)
    rh = super.parse_ports(port_str)
    rh[:type]   = Logic
    return rh
end

Instance Method Details

#[](a, b = nil) ⇒ Object 



57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
 
# File 'lib/tdl/elements/logic.rb', line 57

def [](a,b=nil)
    # if dimension.empty?
    #     if a.eql?(:all)
    #         square = ""
    #     elsif b
    #         square = "[#{a}:#{b}]"
    #     else
    #         square = "[#{a}]"
    #     end

    #     if @port
    #         NqString.new("#{@name.to_s}#{square}")
    #     else
    #         NqString.new("#{name}#{square}")
    #     end
    # else

    if a.is_a? ClassHDL::OpertorChain
        a.slaver = true
    end

    if b.is_a? ClassHDL::OpertorChain
        b.slaver = true
    end

    
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
        TdlSpace::ArrayChain.create(obj: self,lchain: a, end_slice: b, belong_to_module: belong_to_module)
    end
end

#[]=(a, b = nil, c) ⇒ Object 



88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
 
# File 'lib/tdl/elements/logic.rb', line 88

def []=(a,b=nil,c)
    if a.is_a? ClassHDL::OpertorChain
        a.slaver = true
    end

    if b.is_a? ClassHDL::OpertorChain
        b.slaver = true
    end

    # b = a unless b
    if c.is_a? Logic
        cstr = c.signal
    elsif c.is_a? String
        cstr = c
    else
        ""
    end

    lbd = "assign #{self.[](a,b)} = #{cstr};"
    # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.pre_inst << lambda do
    #     lbd
    # end
    belong_to_module.Logic_draw << lbd
    return lbd
end

#active ⇒ Object 



53
54
55
 
# File 'lib/tdl/elements/logic.rb', line 53

def active
    "low"
end

#broaden_and_cross_clk(phase: "POSITIVE", len: 4, lat: 2, wclk: nil, rclk: nil, wreset: "1'b1".to_nq, rreset: "1'b1".to_nq, name: nil) ⇒ Object 



80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
 
# File 'lib/tdl/Logic/logic_latency.rb', line 80

def broaden_and_cross_clk(phase: "POSITIVE",len:4,lat:2,wclk: nil,rclk: nil,wreset: "1'b1".to_nq,rreset: "1'b1".to_nq,name: nil)
    new_l = nil
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
        if wclk.nil? || rclk.nil?
            raise TdlError.new("\n #{self.to_s} BROADEN_AND_CROSS_CLK <clock = nil> \n")
        end
        new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:1)
        large_name_len(phase,len,wclk,wreset,rclk,rreset)
body =
"
broaden_and_cross_clk #(
.PHASE     (#{align_signal(phase)}),  //POSITIVE NEGATIVE
.LEN       (#{align_signal(len)}),
.LAT       (#{align_signal(lat)})
)#{new_l.signal}_inst_#{belong_to_module._auto_name_incr_index_()}(
/* input    */  .rclk       (#{align_signal(rclk,q_mark=false)}),
/* input    */  .rd_rst_n   (#{align_signal(rreset,q_mark=false)}),
/* input    */  .wclk       (#{align_signal(wclk,q_mark=false)}),
/* input    */  .wr_rst_n   (#{align_signal(wreset,q_mark=false)}),
/* input    */  .d          (#{align_signal(self,q_mark=false)}),
/* output   */  .q          (#{align_signal(new_l,q_mark=false)})
);
"
        belong_to_module.Logic_draw << page(tag:"BROADEN_AND_CROSS_CLK",body:body)
    end

    return new_l
end

#copy(name: @name.to_s, dsize: @dsize, port: @port, default: @default, msb_high: @msb_high, dimension: @dimension, type: @type, belong_to_module: @belong_to_module) ⇒ Object 



48
49
50
51
 
# File 'lib/tdl/elements/logic.rb', line 48

def copy(name:@name.to_s,dsize:@dsize,port:@port,default:@default,msb_high:@msb_high,dimension:@dimension,type:@type,belong_to_module:@belong_to_module)
    append_name = name_copy(name)
    belong_to_module.Def.logic(name:append_name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type)
end

#cross_clock(clock: nil, name: false) ⇒ Object

Raises:



48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
 
# File 'lib/tdl/Logic/logic_latency.rb', line 48

def cross_clock(clock:nil,name: false)
    raise TdlError.new("\n #{signal} CROSS CLOCK <clock = nil> \n") unless clock

    # new_l = Logic.new(name:"#{signal(square:false)}_cc",dsize:self.dsize)
    new_l = nil
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
        unless name
            new_l = belong_to_module.Def.logic(name:"#{signal(square:false)}_cc",dsize:self.dsize)
        else
            new_l = belong_to_module.Def.logic(name: name.to_s ,dsize:self.dsize)
        end
        str = %Q{
//----->> #{signal} cross clock <<------------------
cross_clk_sync #(
	.LAT   (2      ),
	.DSIZE (#{dsize})
)#{signal(square:false)}_cross_clk_#{name ? name.to_s : '' }inst(
/* input              */ .clk       (#{align_signal(clock)}),
/* input              */ .rst_n     (#{align_signal("1'b1")}),
/* input [DSIZE-1:0]  */ .d         (#{align_signal(self)}),
/* output[DSIZE-1:0]  */ .q         (#{align_signal(new_l)})
);
//-----<< #{signal} cross clock >>------------------
}
        # @@logic_expression << lambda{ str }
        # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ str }
        belong_to_module.Logic_draw << str
    end

    return new_l
end

#destruct_to(*args) ⇒ Object 



248
249
250
251
252
253
254
 
# File 'lib/tdl/elements/logic.rb', line 248

def destruct_to(*args)
    m = args.map do |e|
        align_signal(e)
    end
    # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.inst_stack += "\nassign #{signal} = {#{m.join(',')}};\n"
    belong_to_module.Logic_draw << "\nassign {#{m.join(',')}} = #{signal};\n"
end

#exp_element(b) ⇒ Object

def signal_proc(a)

if a.is_a? Proc
    a.call
else
    a.to_s
end

end



157
158
159
160
161
162
163
 
# File 'lib/tdl/Logic/logic_main.rb', line 157

def exp_element(b)
    if b.is_a? Proc
        b.call
    else
        b.to_s
    end
end

#falling(cnt: 1, clock: nil, reset: nil) ⇒ Object 



55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
 
# File 'lib/tdl/Logic/logic_edge.rb', line 55

def falling(cnt:1,clock:nil,reset:nil)
    @logic_expression_record ||= Hash.new
    @clock = clock if clock
    @reset = reset if reset
    head_str = ""
    end_str = ""
    str = ""
    # RedefOpertor.with_normal_operators do
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do

        head_str =
        "\n//====>>>> #{signal} FEDGE <<<<#{"="*(60-6-signal.length)}\n"
        end_str =
        "//----<<<< #{signal} FEDGE >>>>#{"-"*(60-6-signal.length)}\n"
    # end
        # @@logic_expression << lambda{ head_str }
        # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ head_str }
        belong_to_module.Logic_draw << head_str

        inst_edge(@clock,@reset)
        if cnt>1
            inst_fall_edge_cnt(cnt-1)
            str =  inst_cnt_edge_signal(cnt-1,:fall)
        else
            str = "#{signal}_falling"
        end
        # @@logic_expression << lambda{ end_str }
        # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ end_str }
        belong_to_module.Logic_draw << end_str
    end
    return str.to_nq
end

#force_nege_index(bool = true) ⇒ Object 



143
144
145
 
# File 'lib/tdl/elements/logic.rb', line 143

def force_nege_index(bool=true)
    @nege_index = bool
end

#init_assign(value) ⇒ Object 



13
14
15
16
17
18
19
20
 
# File 'lib/tdl/bfm/logic_initial_block.rb', line 13

def init_assign(value)
    vstr = RedefOpertor.with_normal_operators do
        with_new_align(0) do
            align_signal(value,q_mark=false)
        end
    end
    @_init_exec_stack << "#{logic_init_tap}#{signal} = #{vstr};\n"
end

#init_exec(str) ⇒ Object 



22
23
24
 
# File 'lib/tdl/bfm/logic_initial_block.rb', line 22

def init_exec(str)
    @_init_exec_stack << "#{logic_init_tap}#{str};\n"
end

#Initial {|_self| ... } ⇒ Object

Yields:

  • (_self)

Yield Parameters:

  • _self (Logic) —

    the object that the method was called on



4
5
6
7
8
9
10
11
 
# File 'lib/tdl/bfm/logic_initial_block.rb', line 4

def Initial(&block)
    @_lg_init_tap_cnt_ = 1
    @_init_exec_stack = []
    yield(self)
    str = initial_block(@_init_exec_stack.join())
    # Logic.add_ex_expression(lambda { str })
    belong_to_module.Logic_draw << str
end

#inst ⇒ Object 



147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
 
# File 'lib/tdl/elements/logic.rb', line 147

def inst
    # if (@port != :origin)
    #     lname = "#{name}_id#{@id}"
    # else
    #     lname = @name.to_s
    # end
    lname = @name.to_s

    unless @ghost
        if dsize.eql?(1) && dimension.empty? 
            str = "#{@type} #{lname}#{@default ? " = #{align_signal(@default)};" : ";"}"
        else
            if (@dsize.is_a? Numeric) && @dsize < 0
                str = "#{@type} [0:#{(-@dsize-1)}] #{lname}#{array_inst} #{@default ? " = #{align_signal(@default)};" : ";"}"
            elsif @nege_index
                str = "#{@type} [0:#{@dsize}-1] #{lname}#{array_inst} #{@default ? " = #{align_signal(@default)};" : ";"}"
            else
                str = "#{@type} [#{@dsize}-1:0]  #{lname}#{array_inst} #{@default ? " = #{align_signal(@default)};" : ";"}"
            end
        end
    else
        str = ""
    end
    str
end

#inst_port ⇒ Object 



187
188
189
190
191
192
193
194
195
196
 
# File 'lib/tdl/elements/logic.rb', line 187

def inst_port

    if dsize.eql? 1
        n = " #{@type}"
    else
        n = " #{@type}[#{(@dsize-1)}:0]"
    end

    return [@port.to_s + n, @name.to_s,array_inst]
end

#latency(count: 1, clock: nil, reset: nil) ⇒ Object 



3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
 
# File 'lib/tdl/Logic/logic_latency.rb', line 3

def latency(count:1,clock:nil,reset:nil)

    unless clock
        sclk = @__clock__
    else
        sclk = clock
    end

    unless reset
        srst = @__reset__
    else
        srst = reset
    end

    unless sclk
        raise TdlError.new("latency clock is nil")
    end 

    unless srst
        raise TdlError.new('latency reset is nil')
    end

    # new_l = Logic.new(name:" #{signal(square:false)}_lat",dsize:self.dsize)
    new_l = belong_to_module.Def.logic(name:"#{signal(square:false)}_lat",dsize:self.dsize)
    str = %Q{
//----->> #{signal} LAST DELAY <<------------------
latency #(
.LAT    (#{count}),
.DSIZE  (#{dsize})
)#{signal(square:false)}_lat#{count}_inst(
#{sclk},
#{srst},
#{signal},
#{new_l.signal}
);
//-----<< #{signal} LAST DELAY >>------------------
}

    # @@logic_expression << lambda{ str }
    # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ str }
    belong_to_module.Logic_draw << str

    return new_l
end

#merge_from(*args) ⇒ Object

def self.clear

@@id = 1
@@inst_stack = []
@@ports = []
@@nc = self.new
BaseElm.recfg_nc(@@nc)

end



240
241
242
243
244
245
246
 
# File 'lib/tdl/elements/logic.rb', line 240

def merge_from(*args)
    m = args.map do |e|
        align_signal(e)
    end
    # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.inst_stack += "\nassign #{signal} = {#{m.join(',')}};\n"
    belong_to_module.Logic_draw << "\nassign #{signal} = {#{m.join(',')}};\n"
end

#port_length ⇒ Object 



173
174
175
176
177
178
179
180
181
182
183
184
185
 
# File 'lib/tdl/elements/logic.rb', line 173

def port_length
    if dsize.eql? 1
        n = ""
    else
        if @dsize.is_a? Numeric
            n = "[#{(@dsize.abs-1)}:0]"
        else
            n = "[#{(@dsize.to_s-1)}:0]"
        end
    end

    (@port.to_s + n +  " ").length
end

#raising(name: nil, cnt: 1, clock: nil, reset: 1.b1) ⇒ Object 



4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
 
# File 'lib/tdl/Logic/logic_edge.rb', line 4

def raising(name: nil, cnt: 1,clock: nil,reset: 1.b1 )

    # if cnt==1 && clock == nil && reset==nil && @raising_record
    #     return @raising_record
    # end

    @logic_expression_record ||= Hash.new
    str = ""
    # RedefOpertor.with_normal_operators do
        @clock = clock if clock
        @reset = reset if reset

        head_str = ""
        end_str = ""
        # RedefOpertor.with_normal_operators do
        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
            head_str =
            "\n//====>>>> #{signal} RAISING EDGE <<<<#{"="*(60-6-signal.length)}\n"
            end_str =
            "\n//----<<<< #{signal} RAISING EDGE >>>>#{"-"*(60-6-signal.length)}\n"

            # @@logic_expression << lambda{ head_str }
            # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ head_str }
            belong_to_module.Logic_draw << head_str
            inst_edge(@clock,@reset)
            unless name 
                if cnt>1
                    inst_raise_edge_cnt(cnt-1)
                    str = inst_cnt_edge_signal(cnt-1,:raise)
                else
                    str = "#{signal}_raising"
                
                end
            else 
                if cnt>1
                    inst_raise_edge_cnt(cnt-1)
                end
                str = name 
            end
            # @@logic_expression << lambda{ end_str }
            # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ end_str }
            belong_to_module.Logic_draw << end_str
        end

    # if cnt==1 && clock == nil && reset==nil
    #     @raising_record = str.to_nq
    # end

    return str.to_nq
end

#repeat(num = 0, &block) ⇒ Object 



26
27
28
29
30
31
32
33
34
35
36
 
# File 'lib/tdl/bfm/logic_initial_block.rb', line 26

def repeat(num=0,&block)
    if num > 0
        @_init_exec_stack << "#{logic_init_tap}repeat(#{num.to_s}) begin\n"
    else
        @_init_exec_stack << "#{logic_init_tap}forever begin\n"
    end
    @_lg_init_tap_cnt_ += 1
    yield
    @_lg_init_tap_cnt_ -= 1
    @_init_exec_stack << "#{logic_init_tap}end\n"
end

#signal(h: nil, l: 0, square: true) ⇒ Object 



114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
 
# File 'lib/tdl/elements/logic.rb', line 114

def signal(h:nil,l:0,square:true)
    if h.is_a? Numeric
        if @dsize.is_a?(Numeric) && (h > @dsize-1)
            h = @dsize - 1
        end
        h = h
    elsif @dsize.is_a? Numeric
        h = (@dsize.abs-1)
    else
        h = "#{@dsize}-1"
    end

    if @port
        NqString.new (@name.to_s)
    elsif !square || @dimension.any?
        NqString.new("#{name}")
    elsif dsize.eql? 1
        NqString.new("#{name}")
    else
        NqString.new("#{name}[#{h}:#{l}]")
    end
end

#to_s ⇒ Object 



137
138
139
140
141
 
# File 'lib/tdl/elements/logic.rb', line 137

def to_s
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
        signal(square:false)
    end
end

#to_sim_source_coe(data: (0...100).to_a, posedge: nil, negedge: nil, loop_coe: true) ⇒ Object

Raises:



58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
 
# File 'lib/tdl/exlib/logic_verify.rb', line 58

def to_sim_source_coe(data: (0...100).to_a, posedge: nil ,negedge: nil ,loop_coe: true)
    raise TdlError.new(" posedge negedge both nil") unless (posedge || negedge )
    # raise TdlError.new "file cant be empty"  unless file

    file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{@belong_to_module._auto_name_incr_index_}.coe")
    _len = 1000
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
        require_hdl 'logic_sim_model.sv'
        itr = AxiTdl::LogicVerify::Iteration.new(length: data.size, data: data )
        File.open(file,'w') do |f|
            f.puts itr.coe
        end
        _len = itr.context.size
    end

    @belong_to_module.instance_exec(self,_len, posedge || 1.b0 , negedge || 1.b0 ,file, loop_coe) do |_self,_len,next_at_posedge_of,next_at_negedge_of,file,loop_coe|
        Instance(:logic_sim_model, "#{_self.name}_sim_model_inst") do |h|
            h.param.LOOP                (loop_coe ? "TRUE" : "FALSE")
            h.param.DSIZE           _self.dsize
            h.param.RAM_DEPTH       _len
            h.input.next_at_negedge_of  next_at_negedge_of
            h.input.next_at_posedge_of  next_at_posedge_of
            h.input.load_trigger        1.b0
            h.input[32].total_length    _len
            h.input[512*8].mem_file     File.expand_path(file)
            h.output['DSIZE'].data      _self
        end

    end
end