Class: Reset
- Inherits:
-
SignalElm
- Object
- AxiTdl::SdlModuleActiveBaseElm
- BaseElm
- SignalElm
- Reset
- Includes:
- BaseModule, ClassHDL::AssignDefOpertor
- Defined in:
- lib/tdl/elements/Reset.rb,
lib/tdl/exlib/clock_reset_verify.rb,
lib/tdl/class_hdl/hdl_redefine_opertor.rb
Overview
require_relative “./tdlerror” require_relative “./basefunc”
Constant Summary
Constants included from ClassHDL::AssignDefOpertor
ClassHDL::AssignDefOpertor::OP_SYMBOLS
Instance Attribute Summary collapse
-
#active ⇒ Object
readonly
Returns the value of attribute active.
-
#dsize ⇒ Object
Returns the value of attribute dsize.
-
#ghost ⇒ Object
Returns the value of attribute ghost.
-
#id ⇒ Object
Returns the value of attribute id.
-
#name ⇒ Object
readonly
Returns the value of attribute name.
-
#port ⇒ Object
Returns the value of attribute port.
Attributes inherited from BaseElm
Class Method Summary collapse
-
.parse_ports(port_str) ⇒ Object
parse text for autogen method and constant ###.
Instance Method Summary collapse
- #high_signal ⇒ Object
-
#initialize(name: "system_rst", active: "LOW", port: false, dsize: 1, belong_to_module: nil) ⇒ Reset
constructor
A new instance of Reset.
-
#inst_port ⇒ Object
def port_length (@port.to_s + “ ”).length end.
-
#low_signal ⇒ Object
def left_port_length (“/* input” + “ */ ”).length end.
- #to_sim_source(ns = 100) ⇒ Object
Methods included from ClassHDL::AssignDefOpertor
curr_assign_block, curr_assign_block=, curr_assign_block_stack, curr_opertor_stack, included, init_op_methods, use_new_yield_opertors, use_old_cond_opertors, with_new_assign_block, with_new_opertor, with_normal_opertor, with_rollback_opertors
Methods included from BaseModule
Methods inherited from SignalElm
#[], inherited, #inst, subclass
Methods inherited from BaseElm
#matrix, #name_copy, #path_refs, recfg_nc, #s, #signal
Methods included from TdlSpace::ExCreateTP
Methods included from AxiTdl::TestUnitTrack
Constructor Details
#initialize(name: "system_rst", active: "LOW", port: false, dsize: 1, belong_to_module: nil) ⇒ Reset
Returns a new instance of Reset.
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# File 'lib/tdl/elements/Reset.rb', line 8 def initialize(name:"system_rst",active:"LOW",port:false,dsize:1, belong_to_module: nil) name_legal?(name) # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Reset.id @dsize = dsize @name = name @port = port @active = active.to_s.downcase if @active.eql?("low") && @active.eql?("high") raise TdlError.new("RESET ACTIVE PARA #{@active} ERROR") end @belong_to_module = belong_to_module unless @belong_to_module raise TdlError.new("Reset<#{name}> dnot have belong_to_module") end end |
Instance Attribute Details
#active ⇒ Object (readonly)
Returns the value of attribute active.
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# File 'lib/tdl/elements/Reset.rb', line 5 def active @active end |
#dsize ⇒ Object
Returns the value of attribute dsize.
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# File 'lib/tdl/elements/Reset.rb', line 6 def dsize @dsize end |
#ghost ⇒ Object
Returns the value of attribute ghost.
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# File 'lib/tdl/elements/Reset.rb', line 6 def ghost @ghost end |
#id ⇒ Object
Returns the value of attribute id.
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# File 'lib/tdl/elements/Reset.rb', line 6 def id @id end |
#name ⇒ Object (readonly)
Returns the value of attribute name.
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# File 'lib/tdl/elements/Reset.rb', line 5 def name @name end |
#port ⇒ Object
Returns the value of attribute port.
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# File 'lib/tdl/elements/Reset.rb', line 6 def port @port end |
Class Method Details
.parse_ports(port_str) ⇒ Object
parse text for autogen method and constant ###
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# File 'lib/tdl/elements/Reset.rb', line 142 def self.parse_ports(port_str) rh = super.parse_ports(port_str) rh[:type] = Reset return rh end |
Instance Method Details
#high_signal ⇒ Object
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# File 'lib/tdl/elements/Reset.rb', line 89 def high_signal if(active.eql? "low") NqString.new("~").concat signal else signal end end |
#inst_port ⇒ Object
def port_length
(@port.to_s + " ").length
end
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# File 'lib/tdl/elements/Reset.rb', line 40 def inst_port # if @port # (@port.to_s + " " + " "*sub_len + @name.to_s) # end if dsize.eql? 1 n = "" else n = "[#{(@dsize-1)}:0]" end return [@port.to_s+n,@name.to_s,""] end |
#low_signal ⇒ Object
def left_port_length
("/* input" + " */ ").length
end
def right_port_length
(".#{@name.to_s} ").length
end
def ex_port(left_align_len = 7,right_align_len = 7)
if left_align_len >= left_port_length
sub_left_len = left_align_len - left_port_length
else
sub_left_len = 0
end
if right_align_len >= right_port_length
sub_right_len = right_align_len - right_port_length
else
sub_right_len = 0
end
if @port
("/* input" + " "*sub_left_len + "*/ " + "."+@name.to_s + " "*sub_right_len)
end
end
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# File 'lib/tdl/elements/Reset.rb', line 81 def low_signal if(active.eql? "low") signal else NqString.new("~").concat signal end end |
#to_sim_source(ns = 100) ⇒ Object
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# File 'lib/tdl/exlib/clock_reset_verify.rb', line 17 def to_sim_source(ns=100) @belong_to_module.instance_exec(self,ns) do |_self,ns| _xxx = (_self.active == 'low') ? 1.b0 : 1.b1 Initial do _self <= _xxx initial_exec("#(#{ns}ns)") _self <= ~_self end end end |