Class: TopModule

Inherits:
SdlModule show all
Defined in:
lib/tdl/sdlmodule/top_module.rb,
lib/tdl/sdlmodule/top_module.rb,
lib/tdl/sdlmodule/top_module.rb,
lib/tdl/exlib/sdlmodule_sim.bak.rb,
lib/tdl/sdlmodule/test_unit_module.rb

Overview

添加 missing

Constant Summary collapse

@@curr_top_module = 
nil

Instance Attribute Summary collapse

Attributes inherited from SdlModule

#create_tcl, #dont_gen_sv, #ex_down_code, #ex_param, #ex_port, #ex_up_code, #head_import_packages, #instance_and_children_module, #instanced_and_parent_module, #module_name, #origin_sv, #out_sv_path, #path, #real_sv_path, #target_class

Class Method Summary collapse

Instance Method Summary collapse

Methods inherited from SdlModule

#<<, #>>, #Always, #AlwaysComb, #Always_comb, #Always_ff, #Assign, #CASE, #CASEX, #CommonCFGReg, #DEFAULT, #Def, #ELSE, #ELSIF, #FOR, #FOREACH, #IF, #Initial, #Instance, #Itgt_Instance, Main, #NameSpaceAdd, #Parameter, #Parameters, #StateMachine, #TrackInf, #TryDef, #WHEN, #__contain_hdl__, #__ref_children_modules__, #_auto_name_incr_index_, #add_children_modules, #add_parent_modules, #add_to_dve_wave, #add_to_new_module, #all_ref_sdlmodules, allmodule_name, #always_ff, #always_sim, #assert, #assert_error, #assert_format_error, #assert_old, base_hdl_ref, #bits, #build_module, #build_module_verb, #call_instance, call_module, #children_inst_tree, #clog2, #contain_hdl, #debugLogic, #def_struct, #define_ele, echo_tracked_by_dve, #enum, exist_module?, #function, #gen_dev_wave_tcl, gen_dev_wave_tcl, gen_sv_module, #generate, #genvar, #has_inward_inst?, #has_signal?, #implicit_inst_module_method_missing, #initial, #initial_exec, #inout, #input, #instance_draw, #instanced, #inward_inst, #localparam, #logic, #logic_bind_, #macro_add_vcs, #macro_def, #method_missing, #negedge, #output, #parameter, #parents_inst_tree, #path_refs, #port, #posedge, #pretty_ref_hdl_moduls_echo, #ref_modules, #require_hdl, #require_package, #root_ref, #rubyOP, #same_clock_domain, #show_ports, #signal, #top_module_ref?, #top_tb_ref?, #track_signals_hash, tracked_by_dve, #tracked_by_dve, #try_call_ele, #urandom_range, #var_common, #vars_define_inst, #vars_exec_inst, #vcs_string, #verify

Constructor Details

#initialize(name: "tdlmodule", out_sv_path: nil) ⇒ TopModule

Returns a new instance of TopModule.



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# File 'lib/tdl/sdlmodule/top_module.rb', line 6

def initialize(name:"tdlmodule",out_sv_path:nil)
    @@curr_top_module = self
    # set sim env
    @sim = TopModule.sim
    @out_sv_path = out_sv_path
    # console_argvs
    # TopModule.sim = @sim
    @constraint = ConstraintsVerb.new

    if @sim
        rewrite_to_warning(out_sv_path,"#{name}.sv")

        name = "#{name}_sim"
    else
        rewrite_to_warning(out_sv_path,"#{name}_sim.sv")
    end

    @techbench = TechBenchModule.new(name:"tb_#{name}",out_sv_path:out_sv_path)
    rtl_top_module = super(name:name,out_sv_path:out_sv_path)
    @techbench.Instance(name,"rtl_top")
    rtl_top_module
end

Dynamic Method Handling

This class handles dynamic methods through the method_missing method in the class SdlModule

Instance Attribute Details

#constraint ⇒ Object

Returns the value of attribute constraint.



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# File 'lib/tdl/sdlmodule/top_module.rb', line 4

def constraint
  @constraint
end

#implicit_itgt_collect ⇒ Object

Returns the value of attribute implicit_itgt_collect.



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# File 'lib/tdl/sdlmodule/top_module.rb', line 349

def implicit_itgt_collect
  @implicit_itgt_collect
end

#sim ⇒ Object

Returns the value of attribute sim.



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# File 'lib/tdl/sdlmodule/top_module.rb', line 4

def sim
  @sim
end

#techbench ⇒ Object

Returns the value of attribute techbench.



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# File 'lib/tdl/sdlmodule/top_module.rb', line 4

def techbench
  @techbench
end

#vcs_path ⇒ Object

vcs path



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# File 'lib/tdl/sdlmodule/top_module.rb', line 416

def vcs_path
  @vcs_path
end

Class Method Details

.contain_hdl(*hdl_paths) ⇒ Object 



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# File 'lib/tdl/auto_script/import_hdl.rb', line 44

def TopModule.contain_hdl(*hdl_paths)
    hdl_paths.each do |hdl_path|
        rel = find_first_hdl_path(hdl_path)
        unless rel 
            return nil 
        end
        unless  $__contain_hdl__.include? rel
            $__contain_hdl__ << rel
        end
    end
end

.current ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 29

def self.current
    @@curr_top_module
end

.define_global(name, default_value) ⇒ Object

def self.recur_ref(sdlmodule,collect_str)

if sdlmodule.is_a? TopModule
    @@root_ref_array << "$root.#{sdlmodule.techbench.module_name}.#{sdlmodule.instanced_and_parent_module.keys.first}.#{collect_str}"
else
    return nil unless sdlmodule.instanced_and_parent_module
    sdlmodule.instanced_and_parent_module.each do |k_inst,v_module|
        next_collect_str = "#{k_inst}.#{collect_str}"
        self.recur_ref(v_module,next_collect_str)
    end
end

end



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# File 'lib/tdl/sdlmodule/top_module.rb', line 328

def self.define_global(name,default_value)
    # RedefOpertor.with_normal_operators do
        self.class_variable_set("@@#{name.to_s}",default_value)

        self.define_singleton_method(name.to_s) do
            self.class_variable_get("@@#{name.to_s}")
        end

        self.define_singleton_method("#{name.to_s}=") do |a|
            self.class_variable_set("@@#{name.to_s}",a)
        end
    # end
end

.method_missing(method, *args, &block) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 417

def self.method_missing(method,*args,&block)

    sdlm = TopModule.new(name: method,out_sv_path: args[0])
    @@package_names ||= []
    sdlm.head_import_packages = []
    sdlm.head_import_packages += @@package_names

    @@package_names.each do |e|
        sdlm.require_package(e,false) if e
    end
    @@package_names = []
    sdlm.instance_exec(&block)

    if args[0] && File.exist?(args[0])
        # sdlm.gen_sv_module
        sdlm.gen_sv_module_verb
        unless sdlm.vcs_path
            # sdlm.test_unit.gen_dve_tcl(File.join(args[0],"dve.tcl"))
            SdlModule.gen_dev_wave_tcl File.join(args[0],"dve.tcl")
        else  
            # sdlm.test_unit.gen_dve_tcl(File.join(sdlm.vcs_path,"dve.tcl"))
            SdlModule.gen_dev_wave_tcl File.join(sdlm.vcs_path,"dve.tcl")
        end
        sdlm.create_xdc

        ## 全局contain_hdl 引入到 TopModule
        sdlm.contain_hdl(*$__contain_hdl__)
    else 
        sdlm.origin_sv = true 
    end
    sdlm
end

.with_package(*args) ⇒ Object

定义模块时添加 package



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# File 'lib/tdl/sdlmodule/top_module.rb', line 451

def self.with_package(*args)
    @@package_names += args
    return self 
end

Instance Method Details

#add_itegration(itgt_class, nickname: nil, param: {}, pins_map: {}, implicit: false) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 356

def add_itegration(itgt_class,nickname:nil,param:{},pins_map:{},implicit:false)
    @_itgt_collect_ ||= []
    if pins_map.is_a? Hash
        pins_map_f = pins_map
    else
        pins_map_f = self.pins[pins_map.to_s] || {}
    end

    ist = Kernel.const_get(itgt_class).new(nickname,pins_map_f,self)
    @_itgt_collect_ << ist unless implicit
    # ist.top_module = self
    param.each do |k,v|
        ist.send("#{k}=",v)
    end

    ## 加入新的itgt时，自动link itgt
    # ist.link_eval
    # puts "------------------"
    # ist.names_pool_inst
    ## 如果itgt没有上级 link 和 不是隐性添加 则直接例化
    # if nickname != "implicit"
        col = ist.class.get_itgt_var('itegration_link_collect',[])
        if col && col.empty?
            ist.inst unless ist.init_inst
            ist.init_inst = true
            ist.inst_index = 0
        end
    # end
    # ist.inst
    return ist
end

#add_test_unit(*args) ⇒ Object 



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# File 'lib/tdl/sdlmodule/test_unit_module.rb', line 326

def add_test_unit(*args)
    args.each do |e|
        unless e.is_a? ItegrationTestUnit
            raise TdlError.new(" add_test_unit args<#{e}> must be ItegrationTestUnit ")
        end
    end
    @_test_unit_collect_ ||= []
    @_test_unit_collect_ = @_test_unit_collect_ + args
end

#Clock(name, freqM: 100, port: :input, pin: [], iostd: [], dsize: 1, pin_prop: nil) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 203

def Clock(name,freqM:100,port: :input,pin:[],iostd:[],dsize:1,pin_prop:nil)
    pin,iostd,pulltype,drive = parse_pin_prop(pin_prop) if pin_prop
    a = super(name,port:port,freqM:freqM,pin:pin,iostd:iostd,dsize:dsize,pin_prop:pin_prop)
    @constraint.add_property(a,pin,iostd,pulltype,drive)
    a
end

#console_argvs ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 64

def console_argvs
    # hash = Parser.parse(ARGV)
    hash = $argvs_hash
    if hash[:sim]
        @sim = hash[:sim]
    end

    bi = Proc.new do
        bp = File.join(@out_sv_path,"program_files/")
        Dir.mkdir(bp) unless File.exist? bp
        bp
    end

    if hash[:gold]
        @constraint.image(type: :gold,next_addr:hash[:next_cfg_addr],bitpath:bi.call)
    elsif hash[:update]
        @constraint.image(type: :update,bitpath:bi.call)
    end
end

#create_add_file_tcl ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 226

def create_add_file_tcl
    return if @sim
    fname = "#{module_name}_add_files.tcl"
    fname = File.join(@out_sv_path,fname)
    File.open(fname,'w') do |f|
        f.puts("add_files \\")
        # f.puts Tdl.all_file_paths.map{ |e| e[1].gsub("\\",'/') }.join("\\\n")
        f.puts Tdl.all_file_paths.map{ |k,v| v.gsub("\\",'/') }.join("\\\n")
    end
end

#create_xdc ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 217

def create_xdc
    return if @sim
    fname = "#{module_name}_constraints.xdc"
    fname = File.join(@out_sv_path,fname)
    File.open(fname,'w') do |f|
        f.puts @constraint.xds
    end
end

#gen_sv_module ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 115

def gen_sv_module
    if @sim
        Tdl.Puts "INFO: JUST GEN SV[#{@module_name}] FOR SIM "
    else
        Tdl.Puts "INFO: JUST GEN TechBench Modules,NO SIM"
    end
    super
    # @techbench.gen_sv_module

    # exec auto gen sub TechBenchModule
    TechBenchModule.gen_sv_module
end

#gen_sv_module_verb ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 170

def gen_sv_module_verb
    mix_itegrations
    ## 添加测试用例 实例化
    _exec_add_test_unit() if TopModule.sim
    
    gen_sv_module
end

#index_inst ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 396

def index_inst
    curr_collect = (implicit_itgt_collect || []) | @_itgt_collect_

    curr_collect.each do |e|
        if e.init_inst
            e.cal_inst_index(0)
        end
    end

    curr_collect = curr_collect.sort { |a, b| a.inst_index <=> b.inst_index }

    curr_collect.each {|e| e.inst unless e.init_inst }

end

#Inout(name, dsize: 1, dimension: [], pin: [], iostd: [], pin_prop: nil) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 196

def Inout(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
    pin,iostd,pulltype,drive = parse_pin_prop(pin_prop) if pin_prop
    a = super(name,dsize:dsize,dimension:dimension,pin:pin,iostd:iostd)
    @constraint.add_property(a,pin,iostd,pulltype,drive)
    a
end

#Input(name, dsize: 1, dimension: [], pin: [], iostd: [], pin_prop: nil) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 182

def Input(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
    pin,iostd,pulltype,drive = parse_pin_prop(pin_prop) if pin_prop
    a = super(name,dsize:dsize,dimension:dimension,pin:pin,iostd:iostd,pin_prop:pin_prop)
    @constraint.add_property(a,pin,iostd,pulltype,drive)
    a
end

#itgt_collect ⇒ Object

attr_accessor :cal_inst_index_proc



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# File 'lib/tdl/sdlmodule/top_module.rb', line 352

def itgt_collect
    @_itgt_collect_
end

#link_eval ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 388

def link_eval
    @_itgt_collect_ ||= []
    
    @_itgt_collect_.each do |i|
        i.link_eval
    end
end

#load_pins(pins_file) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 37

def load_pins(pins_file)
    pins_params = YAML::load(File.open(pins_file))

    pins_params = recur_pins_hash(pins_params)

    pins_params.define_singleton_method("[]") do |index|
        pins_params.fetch(index.to_s)
    end

    @pins_params = pins_params
end

#mix_itegrations ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 128

def mix_itegrations
    ## 执行动态link itgt
    # puts implicit_itgt_collect
    self.link_eval
    self.index_inst
    # if implicit_itgt_collect
    #     ## 执行 itgt inst
    #     implicit_itgt_collect.reverse.each do |itgt|
    #         itgt.inst unless itgt.init_inst
    #     end
    # end
    #
    # ## 执行 itgt inst
    # @_itgt_collect_.each do |itgt|
    #     itgt.inst unless itgt.init_inst
    # end
    ## 执行 itegration_verb 里面的silence
    @_itgt_collect_.each do |itgt|
        itgt.silence_procs_run if itgt.respond_to?('silence_procs_run')
    end

    if implicit_itgt_collect
        ## 执行 itegration_verb 里面的silence
        implicit_itgt_collect.each do |itgt|
            itgt.silence_procs_run if itgt.respond_to?('silence_procs_run')
        end
    end

    ## 生成 itgt下的子模块文件
    # @_itgt_collect_.each do |itgt|
    #     itgt.gen_children_modules()
    # end

    # if implicit_itgt_collect
    #     ## 执行 itegration_verb 里面的silence
    #     implicit_itgt_collect.each do |itgt|
    #         itgt.gen_children_modules()
    #     end
    # end

end

#Output(name, dsize: 1, dimension: [], pin: [], iostd: [], pin_prop: nil) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 189

def Output(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
    pin,iostd,pulltype,drive = parse_pin_prop(pin_prop) if pin_prop
    a = super(name,dsize:dsize,dimension:dimension,pin:pin,iostd:iostd,pin_prop:pin_prop)
    @constraint.add_property(a,pin,iostd,pulltype,drive)
    a
end

#parse_pin_prop(prop = nil) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 178

def parse_pin_prop(prop=nil)
    return [prop["pins"],prop["iostd"],prop["pulltype"],prop["drive"]]
end

#pins ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 33

def pins
    @pins_params
end

#recur_pins_hash(hash) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 49

def recur_pins_hash(hash)
    new_hash = {}
    hash.each do |k,v|
        if v.is_a? Hash
            hash[k] = recur_pins_hash(v)
        else
            if v.is_a?(String) && v=~/\s/
                hash[k] = v.split(/\s+/)
            end
        end
        new_hash[k.to_sym] = hash[k]
    end
    return hash.merge(new_hash)
end

#Reset(name, port: :input, active: "low", pin: [], iostd: [], dsize: 1, pin_prop: nil) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 210

def Reset(name,port: :input,active:"low",pin:[],iostd:[],dsize:1,pin_prop:nil)
    pin,iostd,pulltype,drive = parse_pin_prop(pin_prop) if pin_prop
    a = super(name,port:port,active:active,pin:pin,iostd:iostd,dsize:dsize,pin_prop:pin_prop)
    @constraint.add_property(a,pin,iostd,pulltype,drive)
    a
end

#rewrite_to_warning(path, file_name) ⇒ Object 



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# File 'lib/tdl/sdlmodule/top_module.rb', line 84

def rewrite_to_warning(path,file_name)
    unless path
        _out_sv_path = './'
    else
        _out_sv_path = path
    end

    path_file_name = File.join(_out_sv_path,file_name)

    return unless File.exist? path_file_name

    basename = File.basename(path_file_name,'.sv')

    File.open(path_file_name,'w') do |f|
        str =
"
`timescale 1ns/1ps
module #{basename}();
initial begin
#(1us);
$warning(\"Check TopModule.sim,please!!!\");
$stop;
end
endmodule\n"
        f.puts str
    end

end

#sim_test_hash ⇒ Object 



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# File 'lib/tdl/exlib/sdlmodule_sim.bak.rb', line 340

def sim_test_hash
    TdlSimTest::TdlBaseTestUnit.test_unit_hash
end

#sim_test_hash=(hash) ⇒ Object 



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# File 'lib/tdl/exlib/sdlmodule_sim.bak.rb', line 333

def sim_test_hash=(hash)
    return nil unless TopModule.sim
    rel = TdlSimTest::TdlBaseTestUnit.test_unit_hash || {}
    TdlSimTest::TdlBaseTestUnit.test_unit_hash = rel.merge(hash)
    return TdlSimTest::TdlBaseTestUnit.test_unit_hash
end