Class: TrackInf
- Inherits:
-
CLKInfElm
- Object
- AxiTdl::SdlModuleActiveBaseElm
- BaseElm
- InfElm
- CLKInfElm
- TrackInf
- Extended by:
- BaseFunc
- Includes:
- BaseModule
- Defined in:
- lib/tdl/elements/track_inf.rb,
lib/tdl/elements/track_inf.rb
Overview
signals in interface
Instance Attribute Summary collapse
-
#dsize ⇒ Object
Returns the value of attribute dsize.
-
#enable ⇒ Object
Returns the value of attribute enable.
-
#ghost ⇒ Object
Returns the value of attribute ghost.
-
#id ⇒ Object
Returns the value of attribute id.
-
#name ⇒ Object
Returns the value of attribute name.
-
#port ⇒ Object
Returns the value of attribute port.
-
#tsize ⇒ Object
Returns the value of attribute tsize.
Attributes inherited from CLKInfElm
Attributes inherited from InfElm
Attributes inherited from BaseElm
Class Method Summary collapse
-
.parse_ports(port_array = nil) ⇒ Object
SV FILE PORT PARSE.
-
.sdlinst_t0(ele) ⇒ Object
SdlInst.
Instance Method Summary collapse
- #__inf_signal__(name) ⇒ Object
-
#initialize(name: "t_inf", dsize: 24, tsize: 1, clock: nil, reset: nil, enable: "1'b1".to_nq, port: false, dimension: [], freqM: nil) ⇒ TrackInf
constructor
A new instance of TrackInf.
- #inst ⇒ Object
- #inst_port ⇒ Object
- #track_signals(h = nil, l = nil) ⇒ Object
- #track_trigger(h = nil, l = nil) ⇒ Object
Methods included from BaseFunc
check_same, check_same_class, check_same_clock, check_same_dsize
Methods included from BaseModule
Methods inherited from CLKInfElm
#FreqM, #check_freqM, #clock_reset_taps, #freqM, #freq_align_signal, #intf_def_freqM, #use_which_freq_when_copy
Methods inherited from InfElm
#[], #dimension_num, #draw, inherited, #port_length, same_name_socket, #signal, subclass
Methods inherited from BaseElm
#matrix, #name_copy, #path_refs, recfg_nc, #s, #signal
Methods included from TdlSpace::ExCreateTP
Methods included from AxiTdl::TestUnitTrack
Constructor Details
#initialize(name: "t_inf", dsize: 24, tsize: 1, clock: nil, reset: nil, enable: "1'b1".to_nq, port: false, dimension: [], freqM: nil) ⇒ TrackInf
Returns a new instance of TrackInf.
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# File 'lib/tdl/elements/track_inf.rb', line 10 def initialize(name:"t_inf",dsize:24,tsize:1,clock:nil,reset:nil,enable:"1'b1".to_nq,port:false,dimension:[],freqM:nil) name_legal?(name) super(dimension:dimension,clock:clock,reset:reset,freqM:freqM) @name = name @dsize = dsize @port = port @tsize = tsize @enable = enable end |
Instance Attribute Details
#dsize ⇒ Object
Returns the value of attribute dsize.
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# File 'lib/tdl/elements/track_inf.rb', line 8 def dsize @dsize end |
#enable ⇒ Object
Returns the value of attribute enable.
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# File 'lib/tdl/elements/track_inf.rb', line 8 def enable @enable end |
#ghost ⇒ Object
Returns the value of attribute ghost.
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# File 'lib/tdl/elements/track_inf.rb', line 7 def ghost @ghost end |
#id ⇒ Object
Returns the value of attribute id.
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# File 'lib/tdl/elements/track_inf.rb', line 7 def id @id end |
#name ⇒ Object
Returns the value of attribute name.
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# File 'lib/tdl/elements/track_inf.rb', line 7 def name @name end |
#port ⇒ Object
Returns the value of attribute port.
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# File 'lib/tdl/elements/track_inf.rb', line 8 def port @port end |
#tsize ⇒ Object
Returns the value of attribute tsize.
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# File 'lib/tdl/elements/track_inf.rb', line 8 def tsize @tsize end |
Class Method Details
.parse_ports(port_array = nil) ⇒ Object
SV FILE PORT PARSE
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# File 'lib/tdl/elements/track_inf.rb', line 42 def self.parse_ports(port_array=nil) rep = /(?<up_down>\(\*\s+(?<ud_name>stream_up|stream_down)\s*=\s*"true"\s+\*\))?\s*(track_inf\.)(?<modport>master|slaver)\s+(?<name>\w+)\s*(?<vector>\[.*?\])?/m up_stream_rep = /stream_up/ InfElm.parse_ports(port_array,rep,"track_inf",up_stream_rep) do |h| h[:type] = TrackInf yield h end end |
.sdlinst_t0(ele) ⇒ Object
SdlInst
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# File 'lib/tdl/elements/track_inf.rb', line 54 def self.sdlinst_t0(ele) if ele.class == TrackInf then "track_inf.#{ele.port}" else nil end end |
Instance Method Details
#__inf_signal__(name) ⇒ Object
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# File 'lib/tdl/elements/track_inf.rb', line 66 def __inf_signal__(name) raise TdlError.new("\nARRAY Don't have '#{name}'\n") unless @dimension.empty? # puts "--------------" # puts $new_m.instance_variable_get("@port_axisinfs") # puts "=============" NqString.new(signal.concat ".#{name}") # signal.concat ".#{name}" end |
#inst ⇒ Object
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# File 'lib/tdl/elements/track_inf.rb', line 21 def inst return "" if @ghost || @port with_new_align(0) do if @reset.is_a? SignalElm if @reset.active.casecmp("LOW") == 0 "track_inf #(.DSIZE(#{dsize}),.TSIZE(#{tsize}),.FreqM(#{intf_def_freqM})) #{signal} #{array_inst}(.clock(#{align_signal(@clock,false)}),.rst_n(#{align_signal(@reset,false)}),.enable(#{align_signal(@enable,false)}));" else "track_inf #(.DSIZE(#{dsize}),.TSIZE(#{tsize}),.FreqM(#{intf_def_freqM})) #{signal} #{array_inst}(.clock(#{align_signal(@clock,false)}),.rst_n(!#{align_signal(@reset,false)}),.enable(#{align_signal(@enable,false)}));" end else "track_inf #(.DSIZE(#{dsize}),.TSIZE(#{tsize}),.FreqM(#{intf_def_freqM})) #{signal} #{array_inst}(.clock(#{align_signal(@clock,false)}),.rst_n(#{align_signal(@reset,false)}),.enable(#{align_signal(@enable,false)}));" end end end |
#inst_port ⇒ Object
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# File 'lib/tdl/elements/track_inf.rb', line 36 def inst_port return ["track_inf." + @port.to_s,@name.to_s,array_inst] end |
#track_signals(h = nil, l = nil) ⇒ Object
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# File 'lib/tdl/elements/track_inf.rb', line 104 def track_signals(h=nil,l=nil) raise TdlError.new("\nARRAY Don't have 'track_signals'") unless @dimension.empty? if h.is_a? Range l = h.to_a.min h = h.to_a.max end if h if l sqr = "[#{h.to_s}:#{l.to_s}]" else sqr = "[#{h.to_s}]" end else sqr = "" end NqString.new(signal.concat(".track_signals").concat(sqr)) end |
#track_trigger(h = nil, l = nil) ⇒ Object
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# File 'lib/tdl/elements/track_inf.rb', line 84 def track_trigger(h=nil,l=nil) raise TdlError.new("\nARRAY Don't have 'track_trigger'") unless @dimension.empty? if h.is_a? Range l = h.to_a.min h = h.to_a.max end if h if l sqr = "[#{h.to_s}:#{l.to_s}]" else sqr = "[#{h.to_s}]" end else sqr = "" end NqString.new(signal.concat(".track_trigger").concat(sqr)) end |