Class: OrigenTesters::Test::DUT
- Inherits:
-
Object
- Object
- OrigenTesters::Test::DUT
- Includes:
- Origen::TopLevel, OrigenARMDebug, OrigenJTAG
- Defined in:
- lib/origen_testers/test/dut.rb
Instance Attribute Summary collapse
-
#blocks ⇒ Object
Simple DUT using Nexus interface.
-
#digcap_pins ⇒ Object
Returns the value of attribute digcap_pins.
-
#digcap_settings ⇒ Object
Returns the value of attribute digcap_settings.
-
#digsrc_pins ⇒ Object
Returns the value of attribute digsrc_pins.
-
#digsrc_settings ⇒ Object
Returns the value of attribute digsrc_settings.
-
#hv_supply_pin ⇒ Object
Returns the value of attribute hv_supply_pin.
-
#lv_supply_pin ⇒ Object
Returns the value of attribute lv_supply_pin.
Instance Method Summary collapse
- #digsrc_overlay(options = {}) ⇒ Object
- #execute(options = {}) ⇒ Object
- #find_block_by_id(id) ⇒ Object
- #handshake(options = {}) ⇒ Object
-
#has_margin0_bug? ⇒ Boolean
dummy flag to check for a particular design bug for this DUT.
-
#initialize(options = {}) ⇒ DUT
constructor
A new instance of DUT.
-
#match(options = {}) ⇒ Object
Match loop functionality.
- #memory_test(options = {}) ⇒ Object
- #read_register(reg, options = {}) ⇒ Object
- #startup(options) ⇒ Object
- #write_register(reg, options = {}) ⇒ Object
Constructor Details
#initialize(options = {}) ⇒ DUT
Returns a new instance of DUT.
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# File 'lib/origen_testers/test/dut.rb', line 18 def initialize( = {}) add_pin :tclk add_pin :tdi add_pin :tdo add_pin :tms # add_pin_group :jtag, :tdi, :tdo, :tms add_power_pin_group :vdd1 add_power_pin_group :vdd2 add_virtual_pin :virtual1, type: :virtual_pin add_virtual_pin :virtual2, type: :ate_ch reg :testme32, 0x007a do |reg| reg.bits 31..16, :portB reg.bits 15..8, :portA reg.bits 1, :done reg.bits 0, :enable end @hv_supply_pin = 'VDDHV' @lv_supply_pin = 'VDDLV' @digsrc_pins = [:tdi, :tms] @digsrc_settings = { digsrc_mode: :parallel, digsrc_bit_order: :msb } @digcap_pins = :tdo @digcap_settings = { digcap_format: :twos_complement } @blocks = [Block.new(0, self), Block.new(1, self), Block.new(2, self)] end |
Instance Attribute Details
#blocks ⇒ Object
Simple DUT using Nexus interface
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# File 'lib/origen_testers/test/dut.rb', line 6 def blocks @blocks end |
#digcap_pins ⇒ Object
Returns the value of attribute digcap_pins.
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# File 'lib/origen_testers/test/dut.rb', line 10 def digcap_pins @digcap_pins end |
#digcap_settings ⇒ Object
Returns the value of attribute digcap_settings.
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# File 'lib/origen_testers/test/dut.rb', line 12 def digcap_settings @digcap_settings end |
#digsrc_pins ⇒ Object
Returns the value of attribute digsrc_pins.
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# File 'lib/origen_testers/test/dut.rb', line 9 def digsrc_pins @digsrc_pins end |
#digsrc_settings ⇒ Object
Returns the value of attribute digsrc_settings.
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# File 'lib/origen_testers/test/dut.rb', line 11 def digsrc_settings @digsrc_settings end |
#hv_supply_pin ⇒ Object
Returns the value of attribute hv_supply_pin.
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# File 'lib/origen_testers/test/dut.rb', line 7 def hv_supply_pin @hv_supply_pin end |
#lv_supply_pin ⇒ Object
Returns the value of attribute lv_supply_pin.
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# File 'lib/origen_testers/test/dut.rb', line 8 def lv_supply_pin @lv_supply_pin end |
Instance Method Details
#digsrc_overlay(options = {}) ⇒ Object
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# File 'lib/origen_testers/test/dut.rb', line 170 def ( = {}) = { define: false, # whether to define subr or call it subr_name: false, # default use match type as subr name digsrc_pins: @digsrc_pins, # defaults to what's defined in $dut overlay_reg: nil, # defaults to testme32 register overlay_cycle_num: 32, # Only needed if overlay_reg is NOT nil, this specificies how many clk cycles to overlay. }.merge() if [:define] $tester.start_subroutine([:subr_name]) # Start subroutine digsrc_pins = $tester.assign_digsrc_pins([:digsrc_pins]) $tester.digsrc_start(digsrc_pins, dssc_mode: :single) original_pin_states = {} digsrc_pins.each do |pin| original_pin_states.merge!(pin => pin(pin).data) pin(pin).drive_mem end if [:overlay_reg].nil? [:overlay_cycle_num].times do $tester.digsrc_send(digsrc_pins) $tester.cycle end else $tester.dont_compress = true [:overlay_reg].size.times do $tester.digsrc_send(digsrc_pins) $tester.cycle end end original_pin_states.each do |pin, state| pin(pin).drive(state) end $tester.digsrc_stop(digsrc_pins) $tester.cycle $tester.end_subroutine # end subroutine else $tester.cycle $tester.call_subroutine([:subr_name]) end end |
#execute(options = {}) ⇒ Object
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# File 'lib/origen_testers/test/dut.rb', line 56 def execute( = {}) = { define: false, # whether to define subr or call it name: 'executefunc1' }.merge() if [:define] # define subroutine $tester.start_subroutine([:name]) $tester.cycle $tester.end_subroutine $tester.cycle else # call subroutine $tester.cycle $tester.call_subroutine([:name]) $tester.cycle end end |
#find_block_by_id(id) ⇒ Object
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# File 'lib/origen_testers/test/dut.rb', line 232 def find_block_by_id(id) @blocks.find { |block| block.id == id } end |
#handshake(options = {}) ⇒ Object
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# File 'lib/origen_testers/test/dut.rb', line 152 def handshake( = {}) = { define: false, # whether to define subr or call it }.merge() if [:define] $tester.start_subroutine('handshake') $tester.handshake(readcode: 100) $tester.cycle $tester.cycle $tester.cycle $tester.end_subroutine else $tester.cycle $tester.call_subroutine('handshake') end end |
#has_margin0_bug? ⇒ Boolean
dummy flag to check for a particular design bug for this DUT
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# File 'lib/origen_testers/test/dut.rb', line 228 def has_margin0_bug? false end |
#match(options = {}) ⇒ Object
Match loop functionality
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# File 'lib/origen_testers/test/dut.rb', line 76 def match( = {}) = { type: :match_pin, # whether to match DONE bit in register or match pin # :match_done # :match_2pins delay_in_us: 5, # match loop delay define: false, # whether to define subr or call it subr_name: false, # default use match type as subr name }.merge() subr_name = [:subr_name] ? [:subr_name] : [:type].to_s if [:define] $tester.start_subroutine(subr_name) $tester.cycle if [:type] == :match_done # Match DONE bit in register $tester.wait(match: true, time_in_us: [:delay_in_us], global_loops: true, check_for_fails: true, force_fail_on_timeout: true, clr_fail_post_match: true, manual_stop: true) do # Match on reading done bit reg(:testme32).bits(:done).write(1) reg(:testme32).bits(:done).read! end elsif [:type] == :match_pin # Match on TDO pin state $tester.wait(match: true, pin: pin(:tdo), state: :high, time_in_us: [:delay_in_us], global_loops: true, check_for_fails: true, force_fail_on_timeout: true, clr_fail_post_match: true, manual_stop: true) elsif [:type] == :match_2pins # Match on TDO pin state $tester.wait(match: true, pin: pin(:tdo), state: :high, pin2: pin(:tms), state2: :high, time_in_us: [:delay_in_us], global_loops: true, check_for_fails: true, force_fail_on_timeout: true, clr_fail_post_match: true, manual_stop: true) elsif [:type] == :multiple_entries # Match on TDO pin state, with multiple subr entry points $tester.wait(match: true, pin: pin(:tdo), state: :high, time_in_us: [:delay_in_us], global_loops: true, multiple_entries: true, check_for_fails: true, force_fail_on_timeout: true, clr_fail_post_match: true, manual_stop: true) end $tester.cycle $tester.end_subroutine $tester.cycle else # call subroutine $tester.cycle $tester.call_subroutine(subr_name) $tester.cycle end end |
#memory_test(options = {}) ⇒ Object
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# File 'lib/origen_testers/test/dut.rb', line 210 def memory_test( = {}) = { }.merge() $tester.memory_test(inc_counter_x: true, gen_vector: true) $tester.memory_test(inc_counter_y: true, gen_vector: true) $tester.memory_test(init_counter_x: true) $tester.memory_test(inc_counter_x: true, init_counter_y: true) $tester.memory_test(inc_counter_y: true, capture_vector: true) $tester.memory_test(pin: pin(:tdo), pin_data: :expect) end |
#read_register(reg, options = {}) ⇒ Object
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# File 'lib/origen_testers/test/dut.rb', line 52 def read_register(reg, = {}) arm_debug.write_register(reg, ) end |
#startup(options) ⇒ Object
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# File 'lib/origen_testers/test/dut.rb', line 44 def startup() $tester.set_timeset('tp0', 60) end |
#write_register(reg, options = {}) ⇒ Object
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# File 'lib/origen_testers/test/dut.rb', line 48 def write_register(reg, = {}) arm_debug.write_register(reg, ) end |