Class: OrigenVerilog::Verilog::Node

Inherits:
Node
  • Object
show all
Defined in:
lib/origen_verilog/verilog/node.rb

Instance Attribute Summary

Attributes inherited from Node

#file, #input, #interval, #number_of_lines

Instance Method Summary collapse

Methods inherited from Node

#directory, #find, #find_all, #line_number, #text_value, #value

Instance Method Details

#evaluateObject

Evaluates all functions and turns numbers into Ruby literals



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# File 'lib/origen_verilog/verilog/node.rb', line 89

def evaluate
  Evaluator.new.run(self)
end

#instantiates?(module_or_name) ⇒ Boolean

Returns true if the node instantiates the given module node or module name

Returns:

  • (Boolean)


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# File 'lib/origen_verilog/verilog/node.rb', line 28

def instantiates?(module_or_name)
  name = module_or_name.respond_to?(:to_a) ? module_or_name.to_a[0] : module_or_name
  instantiations = find_all(:module_instantiation)
  if instantiations.empty?
    false
  else
    instantiations.any? { |i| i.to_a[0].to_s == name.to_s }
  end
end

#module(name) ⇒ Object

Returns the AST node for the module with the given name



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# File 'lib/origen_verilog/verilog/node.rb', line 39

def module(name)
  find_all(:module_declaration).find { |n| n.to_a[0].to_s == name.to_s }
end

#modulesObject

Returns an array containing the AST node for all modules in the AST



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# File 'lib/origen_verilog/verilog/node.rb', line 15

def modules
  find_all(:module_declaration)
end

#nameObject

Returns the name of the node, will raise an error if called on a node type for which the name extraction is not yet implemented



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# File 'lib/origen_verilog/verilog/node.rb', line 45

def name
  if type == :module_declaration
    to_a[0]
  else
    fail "Don't know how to extract the name from a #{type} node yet!"
  end
end

#pins(options = {}) ⇒ Object

Returns an array containing all input, output and inout AST nodes. Supply analog: true in the options to return only those pins defined as a real/wreal type and digital: true to return only the pins without a real/wreal type.



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# File 'lib/origen_verilog/verilog/node.rb', line 57

def pins(options = {})
  pins = find_all(:input_declaration, :output_declaration, :inout_declaration)
  if options[:analog] || options[:digital]
    wreals = self.wreals.map { |n| n.to_a.last }
    subset = []
    pins.each do |pin|
      if pin.find(:real) || wreals.include?(pin.to_a.last)
        subset << pin if options[:analog]
      else
        subset << pin if options[:digital]
      end
    end
    subset
  else
    pins
  end
end

#process(file = nil, env = {}) ⇒ Object



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# File 'lib/origen_verilog/verilog/node.rb', line 4

def process(file = nil, env = {})
  file, env = nil, file if file.is_a?(Hash)
  ast = Processor.new.run(self, env)
  if file
    Writer.new.run(file, ast)
  else
    ast
  end
end

#to_top_levelObject

Converts a module node to an Origen top-level model.

This will re-load the Origen target with the resultant model instantiated as the global dut object.



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# File 'lib/origen_verilog/verilog/node.rb', line 97

def to_top_level
  unless type == :module_declaration
    fail 'Currently only modules support the to_model method'
  end
  Origen.target.temporary = -> { TopLevel.new(ast: self) }
  Origen.load_target
end

#top_level_modulesObject

Similar to the modules method, but removes any modules which are instantiated within other modules, therefore leaving only those which could be considered top level



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# File 'lib/origen_verilog/verilog/node.rb', line 22

def top_level_modules
  mods = modules
  modules.reject { |m| mods.any? { |mod| mod.instantiates?(m) } }
end

#wrealsObject

Returns an array containing all wire real/wreal declaration AST nodes, which have been declared as part of a module definition, returning something like this:

[
  s(:net_declaration, "real", "vdd")),
  s(:net_declaration, "real", "vddf")),
]


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# File 'lib/origen_verilog/verilog/node.rb', line 81

def wreals
  find_all(:non_port_module_item)
    .map { |item| item.find(:net_declaration) }
    .compact
    .select { |net| net.find(:real) }
end