Module: VerilogTools

Defined in:
lib/HDLRuby/verilog_hruby.rb,
lib/HDLRuby/verilog_parser.rb

Overview

A set of tools for parsing Verilog generation

Defined Under Namespace

Classes: AST, FileError, GenerateError, HDLRubyState, ParseError, Parser

Constant Summary collapse

HDLRubyLevels =

The possible levels in HDLRuby generation.

[ :top, :system, :hdef, :<=, :seq, :par, :timed, :expr ]
NoEventLevels = 
[ :hdef, :<=, :seq, :par, :timed ]
NoTimeLevels = 
[ :hdef, :<=, :seq, :par ]

Class Method Summary collapse

Class Method Details

.get_name(statement) ⇒ Object

Tool for getting the name of a statement if any.



90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
 
# File 'lib/HDLRuby/verilog_hruby.rb', line 90

def self.get_name(statement)
  case statement.type
  when :seq_block, :par_block
    name = statement[0]
    name_txt = name ? name.to_HDLRuby(HDLRubyState::DEFAULT) : ""
    return name_txt
  when :statement
    statement.each do |child|
      next unless child.is_a?(AST)
      seq_par = VerilogTools.get_name(child)
      return seq_par if seq_par
    end
  else
    return ""
  end
end

.get_port_names(ports) ⇒ Object

Tool for gathering the names of ports.



55
56
57
58
59
60
61
62
63
64
65
66
67
 
# File 'lib/HDLRuby/verilog_hruby.rb', line 55

def self.get_port_names(ports)
  return [] unless ports
  return [] if ports.is_a?(AST) and ports.type == :property
  if ports.respond_to?(:map) then
    return ports.map {|p| VerilogTools.get_port_names(p) }.flatten
  else
    if ports.is_a?(String) then
      return [ ports ]
    else
      return []
    end
  end
end

.get_seq_par(statement) ⇒ Object

Tool for checking if a statement is to be seq or par in HDLRuby



71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
 
# File 'lib/HDLRuby/verilog_hruby.rb', line 71

def self.get_seq_par(statement)
  case statement.type
  when :blocking_asignment
    return :seq
  when :non_blocking_assignment
    return :par
  when :statement
    statement.each do |child|
      next unless child.is_a?(AST)
      seq_par = VerilogTools.get_seq_par(child)
      return seq_par if seq_par
    end
    return nil
  else
    return nil
  end
end

.name_to_HDLRuby(name) ⇒ Object

Converts a Verilog HDL name to a HDLRuby one.



109
110
111
112
113
114
115
116
117
118
 
# File 'lib/HDLRuby/verilog_hruby.rb', line 109

def self.name_to_HDLRuby(name)
  if name[0] =~ /[_$A-Z]/ then
    # HDLRuby names cannot start with a $ or a capital letter.
    # To fix that add an "_", but then to avoid confusion, also
    # convert starting "_" to "__" if any.
    return "_" + name
  else
    return name
  end
end

.operator_to_HDLRuby(op) ⇒ Object

Converts a Verilog HDL operator to a HDLRuby one.



136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
 
# File 'lib/HDLRuby/verilog_hruby.rb', line 136

def self.operator_to_HDLRuby(op)
  case op
  when "!"
    return "~"
  when "&&"
    return "&"
  when "||"
    return "|"
  when "~&"
    return ".send(:~) | ~"
  when "~|"
    return ".send(:~) & ~"
  when "~^"
    return "^~"
  when "^|"
    return "^"
  else
    return op
  end
end

.system_to_HDLRuby(name, args) ⇒ Object

Converts a Verilog HDL system task to a HDLRuby one.



121
122
123
124
125
126
127
128
129
130
131
132
 
# File 'lib/HDLRuby/verilog_hruby.rb', line 121

def self.system_to_HDLRuby(name,args)
  case name
  when "$signed"
    return "(#{args}).as(signed[(#{args}).type.width])"
  when "$display"
    return "hprint(#{args})"
  when "$finish"
    return "terminate"
  else
    raise "Internal error: unsupported system task #{name} yet."
  end
end