Class: Clock

Inherits:
SignalElm show all
Includes:
BaseModule, ClassHDL::AssignDefOpertor
Defined in:
lib/tdl/elements/clock.rb,
lib/tdl/elements/clock.rb,
lib/tdl/exlib/clock_reset_verify.rb,
lib/tdl/class_hdl/hdl_redefine_opertor.rb

Overview

require_relative “./tdlerror” require_relative “./basefunc”

Constant Summary

Constants included from ClassHDL::AssignDefOpertor

ClassHDL::AssignDefOpertor::OP_SYMBOLS

Instance Attribute Summary collapse

Attributes inherited from BaseElm

#belong_to_module

Class Method Summary collapse

Instance Method Summary collapse

Methods included from ClassHDL::AssignDefOpertor

curr_assign_block, curr_assign_block=, curr_assign_block_stack, curr_opertor_stack, included, init_op_methods, use_new_yield_opertors, use_old_cond_opertors, with_new_assign_block, with_new_opertor, with_normal_opertor, with_rollback_opertors

Methods included from BaseModule

#length, #to_s

Methods inherited from SignalElm

#[], inherited, #inst, subclass

Methods inherited from BaseElm

#matrix, #name_copy, #path_refs, recfg_nc, #s, #signal

Methods included from TdlSpace::ExCreateTP

#root_ref

Methods included from AxiTdl::TestUnitTrack

#tracked_by_dve

Constructor Details

#initialize(name: "system_clock", freqM: 100.0, port: false, dsize: 1, jitter: 0.01, belong_to_module: nil) ⇒ Clock

Returns a new instance of Clock.



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# File 'lib/tdl/elements/clock.rb', line 8

def initialize(name:"system_clock",freqM:100.0,port:false,dsize:1,jitter: 0.01, belong_to_module: nil)
    name_legal?(name)
    # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Clock.id
    @name = name
    @freqM = freqM
    @port = port
    @dsize = dsize
    @jitter = jitter
    @belong_to_module = belong_to_module
    unless @belong_to_module 
        raise TdlError.new("Clock<#{name}> dnot have belong_to_module")
    end
end

Instance Attribute Details

#dsize ⇒ Object

Returns the value of attribute dsize.



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# File 'lib/tdl/elements/clock.rb', line 6

def dsize
  @dsize
end

#freqM ⇒ Object

Returns the value of attribute freqM.



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# File 'lib/tdl/elements/clock.rb', line 6

def freqM
  @freqM
end

#ghost ⇒ Object

Returns the value of attribute ghost.



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# File 'lib/tdl/elements/clock.rb', line 6

def ghost
  @ghost
end

#id ⇒ Object

Returns the value of attribute id.



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# File 'lib/tdl/elements/clock.rb', line 6

def id
  @id
end

#jitter ⇒ Object

Returns the value of attribute jitter.



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# File 'lib/tdl/elements/clock.rb', line 6

def jitter
  @jitter
end

#name ⇒ Object (readonly)

Returns the value of attribute name.



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# File 'lib/tdl/elements/clock.rb', line 5

def name
  @name
end

#port ⇒ Object

Returns the value of attribute port.



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# File 'lib/tdl/elements/clock.rb', line 6

def port
  @port
end

Class Method Details

.checkpclock(aclk, bclk, blm) ⇒ Object 



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# File 'lib/tdl/elements/clock.rb', line 150

def self.checkpclock(aclk,bclk,blm)
    blm.Clock_draw << self.checkpclockdraw(aclk,bclk,blm)
end

.checkpclockdraw(aclk, bclk, blm) ⇒ Object 



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# File 'lib/tdl/elements/clock.rb', line 154

def self.checkpclockdraw(aclk,bclk,blm)
    @@_cpc_id ||= 0
    cc_done = "cc_done_#{@@_cpc_id}"
    cc_same = "cc_same_#{@@_cpc_id}"
    cc_afreq = "cc_afreq_#{@@_cpc_id}"
    cc_bfreq = "cc_bfreq_#{@@_cpc_id}"
    str =
"//--->> CheckClock <<----------------
logic #{cc_done},#{cc_same};
integer #{cc_afreq},#{cc_bfreq};
ClockSameDomain CheckPClock_inst_#{@@_cpc_id}(
/*  input         */      .aclk     (#{align_signal(aclk,q_mark=false)}),
/*  input         */      .bclk     (#{align_signal(bclk,q_mark=false)}),
/*  output logic  */      .done     (#{cc_done}),
/*  output logic  */      .same     (#{cc_same}),
/*  output integer */     .aFreqK   (#{cc_afreq}),
/*  output integer */     .bFreqK   (#{cc_bfreq})
);

initial begin
wait(#{cc_done});
assert(#{cc_same})
else begin
    $error(\"--- Error : `#{blm.module_name}` clock is not same, #{aclk}< %0f M> != #{bclk}<%0f M>\",1000000.0/#{cc_afreq}, 1000000.0/#{cc_bfreq});
    repeat(10)begin 
        @(posedge #{aclk});
    end
    $stop;
end
end
//---<< CheckClock >>----------------
"
    @@_cpc_id += 1
    str
end

.parse_ports(port_str) ⇒ Object

parse text for autogen method and constant ###



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# File 'lib/tdl/elements/clock.rb', line 131

def self.parse_ports(port_str)
    rh = super.parse_ports(port_str)
    rh[:type]   = Clock
    return rh
end

.same_clock(blm, *clks) ⇒ Object 



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# File 'lib/tdl/elements/clock.rb', line 142

def self.same_clock(blm,*clks)
    blm.Clock_draw << "//-------- CLOCKs Total #{clks.size} ----------------------"
    clks[1,clks.size].each do |c|
        self.checkpclock(clks[0],c,blm)
    end
    blm.Clock_draw << "//======== CLOCKs Total #{clks.size} ======================"
end

Instance Method Details

#inst_port(align_len = 7) ⇒ Object

def port_length

(@port.to_s + " ").length

end



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# File 'lib/tdl/elements/clock.rb', line 26

def inst_port(align_len = 7)
    # if align_len >=  port_length
    #     sub_len = align_len - port_length
    # else
    #     sub_len = 0
    # end
    #
    # if @port
    #     (@port.to_s + " " + " "*sub_len + @name.to_s)
    # end

    if dsize.eql? 1
        n = ""
    else
        n = "[#{(@dsize-1)}:0]"
    end

    return [@port.to_s+n, @name.to_s,""]
end

#to_sim_source ⇒ Object 



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# File 'lib/tdl/exlib/clock_reset_verify.rb', line 4

def to_sim_source
    
    @belong_to_module.instance_exec(self) do |_self|
        Initial do 
            _self   <= 1.b0 
            initial_exec("#(100ns)")
            initial_exec("forever begin #(#{1000.0/_self.freqM/2}ns);#{_self} = ~#{_self};end")
        end
    end
end