Class: SignalElm

Inherits:

BaseElm

• Object
• AxiTdl::SdlModuleActiveBaseElm
• BaseElm
• SignalElm

Defined in:

lib/tdl/elements/originclass.rb,
lib/tdl/class_hdl/hdl_redefine_opertor.rb

Direct Known Subclasses

Clock, Logic, Reset

Constant Summary

@@child =

[]

Instance Attribute Summary

Attributes inherited from BaseElm

#belong_to_module, #name

Class Method Summary

• .inherited(subclass) ⇒ Object
• .parse_ports(port_str) ⇒ Object

  parse text for autogen method and constant ###.

• .subclass ⇒ Object

Instance Method Summary

• #[](a, b = nil) ⇒ Object
• #inst ⇒ Object

Methods inherited from BaseElm

#matrix, #name_copy, #path_refs, recfg_nc, #s, #signal

Methods included from TdlSpace::ExCreateTP

#root_ref

Methods included from AxiTdl::TestUnitTrack

#tracked_by_dve

Class Method Details

.inherited(subclass) ⇒ Object

# File 'lib/tdl/elements/originclass.rb', line 196

def self.inherited(subclass)
    unless @@child.include? subclass
        @@child << subclass
    end
end

.parse_ports(port_str) ⇒ Object

parse text for autogen method and constant ###

# File 'lib/tdl/elements/originclass.rb', line 207

def self.parse_ports(port_str)
    normal_ports = []
    del_ports = []
    if port_str
        normal_ports = port_str.map do |e|
            me = e.match(/(?<in_out>input|output|inout)\s*(logic|wire|reg|bit)?\s*(?<vector>\[.*?\])?\s+(?<name>\w+)\s*(?<array>\[.*?\])?/)
            # me = e.match(/(?<in_out>input|output|inout)\s*(logic|wire)?\s*(?<vector>\[.*?\])?\s*(?<name>\w+)/)
            if me
                del_ports << e
                h = Hash.new
                h[:type] = Logic
                h[:name]    = me["name"].downcase
                h[:origin_name] = me["name"]
                h[:in_out]  = me["in_out"]
                if me["vector"]
                    h[:vector]  = me["vector"]
                end
                if me["array"]
                    h[:array] = me["array"]
                end

                h[:port_left_len] = 4+6+1+(h[:vector] ? h[:vector].length : 0) +6
                h[:port_right_len]= 4+h[:origin_name].length

                h[:inst_ex_port] = lambda { |ml,mr|
                    if ml  >= h[:port_left_len]
                        ll = ml - h[:port_left_len]
                    else
                        ll = 1
                    end

                    if mr  >= h[:port_right_len]
                        rl = mr - h[:port_right_len]
                    else
                        rl = 1
                    end
                    "/*  #{(h[:in_out]=="output") ? h[:in_out] : h[:in_out]+" "} #{h[:vector]}" +" "*(ll) + "*/ " + ".#{h[:origin_name]}"+" "*(rl)+" (\#{align_signal(#{h[:name]},q_mark=false)})"
                }

                yield h

                h
            else
                nil
            end
        end
    end
    return_port_str = port_str - del_ports
    return return_port_str
end

.subclass ⇒ Object

# File 'lib/tdl/elements/originclass.rb', line 202

def self.subclass
    @@child
end

Instance Method Details

#[](a, b = nil) ⇒ Object

# File 'lib/tdl/elements/originclass.rb', line 258

def [](a,b=nil)
    if a.is_a? ClassHDL::OpertorChain
        a.slaver = true
    end

    if b.is_a? ClassHDL::OpertorChain
        b.slaver = true
    end

    # b = a unless b
    if a== :all
        square = ""
    elsif b
        square = "[#{a}:#{b}]"
    else
        square = "[#{a}]"
    end

    NqString.new("#{name}#{square}")
end

#inst ⇒ Object

# File 'lib/tdl/elements/originclass.rb', line 279

def inst
    unless @ghost
        # "logic  #{signal};"
        if dsize.eql?(1)
            "logic  #{signal};"
        else
            if (@dsize.is_a? Numeric) && @dsize < 0
                str = "logic [0:#{(-@dsize-1)}] #{signal};"
            else
                str = "logic [#{(@dsize-1)}:0]  #{signal};"
            end
        end
    else
        ""
    end
end