Class: SdlModule

Inherits:
Object
  • Object
show all
Defined in:
lib/tdl/sdlmodule/sdlmodule.rb,
lib/tdl/elements/track_inf.rb,
lib/tdl/sdlmodule/sdlmodule.rb,
lib/tdl/sdlmodule/sdlmodule.rb,
lib/tdl/class_hdl/hdl_assign.rb,
lib/tdl/class_hdl/hdl_random.rb,
lib/tdl/class_hdl/hdl_struct.rb,
lib/tdl/class_hdl/hdl_verify.rb,
lib/tdl/sdlmodule/top_module.rb,
lib/tdl/class_hdl/hdl_foreach.rb,
lib/tdl/class_hdl/hdl_initial.rb,
lib/tdl/class_hdl/hdl_package.rb,
lib/tdl/class_hdl/hdl_function.rb,
lib/tdl/class_hdl/hdl_generate.rb,
lib/tdl/class_hdl/hdl_always_ff.rb,
lib/tdl/class_hdl/hdl_parameter.rb,
lib/tdl/class_hdl/hdl_module_def.rb,
lib/tdl/class_hdl/hdl_module_def.rb,
lib/tdl/class_hdl/hdl_module_def.rb,
lib/tdl/sdlmodule/sdlmodule_draw.rb,
lib/tdl/sdlmodule/sdlmodule_draw.rb,
lib/tdl/class_hdl/hdl_always_comb.rb,
lib/tdl/class_hdl/hdl_block_ifelse.rb,
lib/tdl/sdlmodule/sdlmodule_varible.rb,
lib/tdl/sdlmodule/sdlmodule_varible.rb,
lib/tdl/sdlmodule/sdlmodule_instance.rb,
lib/tdl/sdlmodule/sdlmodule_instance.rb,
lib/tdl/elements/common_configure_reg.rb,
lib/tdl/class_hdl/hdl_ex_defarraychain.rb,
lib/tdl/class_hdl/hdl_redefine_opertor.rb,
lib/tdl/sdlmodule/sdlmodule_arraychain.rb,
lib/tdl/sdlmodule/sdlmodule_port_define.rb,
lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb

Overview

添加状态机

Constant Summary collapse

@@allmodule_name = 
[]
@@allmodule = 
[]
@@ele_array =

include AlwaysBlock @@ele_array = ([Parameter] | SignalElm.subclass | InfElm.subclass | CLKInfElm.subclass | [MailBox,BfmStream])

([Parameter] | SignalElm.subclass | CLKInfElm.subclass | [MailBox] | ['ExOther'])
@@__foreach_index_cnt__ = 
0
@@__for_index_cnt__ = 
0

Instance Attribute Summary collapse

Class Method Summary collapse

Instance Method Summary collapse

Constructor Details

#initialize(name: "tdlmodule", out_sv_path: nil) ⇒ SdlModule

Returns a new instance of SdlModule.



120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 120

def initialize(name: "tdlmodule",out_sv_path: nil)
    # $new_m = self
    # self.BindEleClassVars = PackClassVars.new
    # GlobalParam.PushTdlModule(self)
    @out_sv_path = out_sv_path
    def_main_method(name)
    @@allmodule << self
    @module_name = name
    @real_sv_path = File.join(@out_sv_path,"#{@module_name}.sv") if @out_sv_path
    # @port_clocks = []
    # @port_resets = []
    # @port_params = []
    # @port_logics = []
    # @port_datainfs = []
    # @port_datainf_c_s = []
    # @port_videoinfs = []
    # @port_axisinfs = []
    # @port_axi4infs = []
    # @port_axilinfs = []

    @port_clocks        = Hash.new
    @port_resets        = Hash.new
    @port_params        = Hash.new
    @port_logics        = Hash.new
    @port_datainfs      = Hash.new
    @port_datainf_c_s   = Hash.new
    @port_videoinfs     = Hash.new
    @port_axisinfs      = Hash.new
    @port_axi4infs      = Hash.new
    @port_axilinfs      = Hash.new

    # @techbench = TechBench.new
    @sub_instanced = []
    ## --------
    @@ele_array.each do |e|
        head_str = "@#{e.to_s}"
        self.instance_variable_set("#{head_str}_collect",[])
        self.instance_variable_set("#{head_str}_inst",[])
        self.instance_variable_set("#{head_str}_draw",[])
        self.instance_variable_set("#{head_str}_pre_inst_stack",[])
        self.instance_variable_set("#{head_str}_post_inst_stack",[])
        # tmp = e.new(name:"#{e.to_s}_NC")
        # tmp.ghost = true
        # self.instance_variable_set("#{head_str}_NC",tmp)
    end
    create_ghost
    # @super_modules = []
    # @Logic_collect = []
    # @Logic_inst = []
    # @Logic_draw = []
    #
    # @Clock_collect = []
    # @Clock_inst = []
    # @Clock_draw = []
    #
    # @Reset_collect = []
    # @Reset_inst = []
    # @Reset_draw = []
    #
    # @Parameter_collect = []
    # @Parameter_inst = []
    # @Parameter_draw = []
    #
    # @DataInf_collect = []
    # @DataInf_inst = []
    # @DataInf_draw = []
    #
    # @DataInf_C_collect = []
    # @DataInf_C_inst = []
    # @DataInf_C_draw = []
    #
    # @AxiStream_collect = []
    # @AxiStream_inst = []
    # @AxiStream_draw = []
    #
    # @AxiLite_collect = []
    # @AxiLite_inst = []
    # @AxiLite_draw = []
    #
    # @VideoInf_collect = []
    # @VideoInf_inst = []
    # @VideoInf_draw = []
    #
    # @Axi4_collect = []
    # @Axi4_inst = []
    # @Axi4_draw = []
    if block_given?
        yield(self)
    end

    @instanced_and_parent_module ||= Hash.new
    @instance_and_children_module ||= Hash.new
end

Dynamic Method Handling

This class handles dynamic methods through the method_missing method

#method_missing(method, *args, &block) ⇒ Object

例化模块



343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 343

def method_missing(method,*args,&block)

    @@_method_missing_sub_methds ||= []

    @@_method_missing_sub_methds.each do |me|
        rel = self.send(me,method,*args,&block)
        if rel 
            return rel 
        end
    end

    ## 最后才调用阴性例化模块
    rel = implicit_inst_module_method_missing(method,*args,&block)
    if rel 
        return rel
    else
        super
    end
end

Instance Attribute Details

#create_tcl ⇒ Object (readonly)

Returns the value of attribute create_tcl.



114
115
116
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 114

def create_tcl
  @create_tcl
end

#dont_gen_sv ⇒ Object

Returns the value of attribute dont_gen_sv.



116
117
118
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 116

def dont_gen_sv
  @dont_gen_sv
end

#ex_down_code ⇒ Object

Returns the value of attribute ex_down_code.



112
113
114
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 112

def ex_down_code
  @ex_down_code
end

#ex_param ⇒ Object

Returns the value of attribute ex_param.



112
113
114
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 112

def ex_param
  @ex_param
end

#ex_port ⇒ Object

Returns the value of attribute ex_port.



112
113
114
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 112

def ex_port
  @ex_port
end

#ex_up_code ⇒ Object

Returns the value of attribute ex_up_code.



112
113
114
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 112

def ex_up_code
  @ex_up_code
end

#head_import_packages ⇒ Object

模块头部添加package引入



118
119
120
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 118

def head_import_packages
  @head_import_packages
end

#instance_and_children_module ⇒ Object

Returns the value of attribute instance_and_children_module.



441
442
443
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 441

def instance_and_children_module
  @instance_and_children_module
end

#instanced_and_parent_module ⇒ Object

attr_accessor :ports attr_accessor :parent_modules,:children_modules



440
441
442
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 440

def instanced_and_parent_module
  @instanced_and_parent_module
end

#module_name ⇒ Object

Returns the value of attribute module_name.



113
114
115
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 113

def module_name
  @module_name
end

#origin_sv ⇒ Object

Returns the value of attribute origin_sv.



16
17
18
 
# File 'lib/tdl/sdlmodule/sdlmodule_draw.rb', line 16

def origin_sv
  @origin_sv
end

#out_sv_path ⇒ Object

Returns the value of attribute out_sv_path.



113
114
115
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 113

def out_sv_path
  @out_sv_path
end

#path ⇒ Object

Returns the value of attribute path.



115
116
117
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 115

def path
  @path
end

#real_sv_path ⇒ Object

Returns the value of attribute real_sv_path.



115
116
117
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 115

def real_sv_path
  @real_sv_path
end

#target_class ⇒ Object

Returns the value of attribute target_class.



116
117
118
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 116

def target_class
  @target_class
end

#techbench ⇒ Object

Returns the value of attribute techbench.



113
114
115
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 113

def techbench
  @techbench
end

Class Method Details

.allmodule_name ⇒ Object 



9
10
11
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 9

def self.allmodule_name
    @@allmodule_name
end

.call_module(module_name) ⇒ Object 



13
14
15
16
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 13

def self.call_module(module_name)
    $__sdl_curr_self__.send(module_name)
    # main.send(module_name)
end

.exist_module?(name) ⇒ Boolean

Returns:

  • (Boolean) 


18
19
20
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 18

def self.exist_module?(name)
    @@allmodule_name.include? name.to_s
end

.gen_sv_module ⇒ Object 



18
19
20
21
22
 
# File 'lib/tdl/sdlmodule/sdlmodule_draw.rb', line 18

def self.gen_sv_module
    @@allmodule.each do |e|
        e.gen_sv_module
    end
end

.Main ⇒ Object 



22
23
24
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 22

def self.Main
    $__sdl_curr_self__
end

Instance Method Details

#<<(*args) ⇒ Object 



369
370
371
372
 
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 369

def <<(*args)
    str = "{<<{#{args.map{|e| e.to_s }.join(',')}}}"
    TdlSpace::ArrayChain.new(str)
end

#>>(*args) ⇒ Object 



364
365
366
367
 
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 364

def >>(*args)
    str = "{>>{#{args.map{|e| e.to_s }.join(',')}}}"
    TdlSpace::ArrayChain.new(str)
end

#add_children_modules(inst_obj: nil, module_poit: nil) ⇒ Object 



543
544
545
546
547
548
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 543

def add_children_modules(inst_obj:nil,module_poit:nil)
    # inst_name = inst_name.to_s
    @instance_and_children_module ||= Hash.new
    @instance_and_children_module[inst_obj] = module_poit
    module_poit.add_parent_modules(inst_obj:inst_obj,module_poit:self)
end

#add_parent_modules(inst_obj: nil, module_poit: nil) ⇒ Object 



552
553
554
555
556
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 552

def add_parent_modules(inst_obj:nil,module_poit:nil)
    # inst_name = inst_name.to_s
    @instanced_and_parent_module ||= Hash.new
    @instanced_and_parent_module[inst_obj] = module_poit
end

#add_to_new_module(variable = "@port_params", new_var) ⇒ Object 



22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
 
# File 'lib/tdl/sdlmodule/sdlmodule_port_define.rb', line 22

def add_to_new_module(variable="@port_params",new_var)
    _vars = self.instance_variable_get(variable)    # get hash

    define_ele(new_var) ## 给sdlmodule 定义方法，方法名为 new_var.name ,返回new_var对象

    @ports ||=Hash.new

    _vars[new_var.name] = new_var
    @ports[new_var.name] = new_var  unless new_var.is_a? Parameter

    new_var.belong_to_module = self

    add_new_after_inst(new_var) ## 当在sdlmodule里面例化 子sdlmodule时可以通过child_sdlmodule_inst[:key] 访问 子模块的port

    return new_var
end

#Always(posedge: nil, negedge: nil, &block) ⇒ Object 



146
147
148
 
# File 'lib/tdl/class_hdl/hdl_always_ff.rb', line 146

def Always(posedge: nil,negedge: nil,&block)
    ClassHDL::AlwaysFF(sdl_m: self,posedge: posedge,negedge: negedge,&block)
end

#Always_comb(&block) ⇒ Object Also known as: always_comb 



49
50
51
 
# File 'lib/tdl/class_hdl/hdl_always_comb.rb', line 49

def Always_comb(&block)
    ClassHDL::AlwaysComb(self,&block)
end

#always_ff(*args, &block) ⇒ Object 



154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
 
# File 'lib/tdl/class_hdl/hdl_always_ff.rb', line 154

def always_ff(*args,&block)
    if args[0].is_a? Hash 
        return Always(args[0],&block)
    end 
    posedge_list = []
    negedge_list = [] 

    args.each do |e|
        if e.is_a? ClassHDL::ClassPosedge
            posedge_list << e 
        elsif e.is_a? ClassHDL::ClassNegedge
            negedge_list << e 
        end
    end

    ClassHDL::AlwaysFF(sdl_m: self,posedge: posedge_list,negedge: negedge_list,&block)
end

#Always_ff(posedge: nil, negedge: nil, &block) ⇒ Object 



150
151
152
 
# File 'lib/tdl/class_hdl/hdl_always_ff.rb', line 150

def Always_ff(posedge: nil,negedge: nil,&block)
    ClassHDL::AlwaysFF(sdl_m: self,posedge: posedge,negedge: negedge,&block)
end

#always_sim(posedge: nil, negedge: nil, &block) ⇒ Object 



172
173
174
 
# File 'lib/tdl/class_hdl/hdl_always_ff.rb', line 172

def always_sim(posedge: nil,negedge: nil,&block)
    ClassHDL::AlwaysSIM(sdl_m: self,posedge: posedge,negedge: negedge,&block)
end

#AlwaysComb(&block) ⇒ Object 



45
46
47
 
# File 'lib/tdl/class_hdl/hdl_always_comb.rb', line 45

def AlwaysComb(&block)
    ClassHDL::AlwaysComb(self,&block)
end

#assert(cond, formats = false, *argsx, &block) ⇒ Object 



77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
 
# File 'lib/tdl/class_hdl/hdl_initial.rb', line 77

def assert(cond,formats=false,*argsx,&block)
    unless formats
        return assert_old(cond,nil,&block)    
    end
    if formats.is_a?(String) && argsx.empty? 
        return assert_old(cond,argv_str=formats,&block)
    end

    new_op = ClassHDL::BlocAssertIF.new
    ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
        if cond.is_a? ClassHDL::OpertorChain
            cond.slaver = true
        end
        ab.cond = cond
        if block_given?
            block.call
        else 
            assert_format_error([formats],argsx)
        end

    end
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
    
    return new_op

end

#assert_error(argv_str) ⇒ Object 



132
133
134
135
 
# File 'lib/tdl/class_hdl/hdl_initial.rb', line 132

def assert_error(argv_str)
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")".to_nq]))
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq]))
end

#assert_format_error(formats = [], args = []) ⇒ Object 



137
138
139
140
 
# File 'lib/tdl/class_hdl/hdl_initial.rb', line 137

def assert_format_error(formats=[],args=[])
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{formats.join(' ')}\",#{args.map{|s| s.to_s}.join(',')})".to_nq]))
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq]))
end

#assert_old(cond, argv_str = nil, &block) ⇒ Object 



104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
 
# File 'lib/tdl/class_hdl/hdl_initial.rb', line 104

def assert_old(cond,argv_str=nil,&block)
    new_op = ClassHDL::BlocAssertIF.new
    # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
    #     new_op.slaver = true
    # end
    ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
        if cond.is_a? ClassHDL::OpertorChain
            cond.slaver = true
        end
        ab.cond = cond
        if block_given?
            block.call
        else 
            if argv_str  
                assert_error(argv_str)
            end
        end

    end
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)

    # unless argv_str
    #     assert_error(argv_str)
    # end
    
    return new_op
end

#Assign(&block) ⇒ Object 



46
47
48
 
# File 'lib/tdl/class_hdl/hdl_assign.rb', line 46

def Assign(&block)
    ClassHDL::Assign(self,&block)
end

#bits(arg) ⇒ Object 



384
385
386
387
 
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 384

def bits(arg)
    str = "$bits(#{arg.to_s})"
    TdlSpace::ArrayChain.new(str)
end

#build_module(ex_param: "", ex_port: "", ex_up_code: "", ex_down_code: "") ⇒ Object 



76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
 
# File 'lib/tdl/sdlmodule/sdlmodule_draw.rb', line 76

def build_module(ex_param:"",ex_port:"",ex_up_code:"",ex_down_code:"")
    # Tdl.Puts pagination(module_name)
    Tdl.Build_SdlModule_Puts(module_name)

    ex_param        = ex_param.to_s     unless ex_param
    ex_port         = ex_port.to_s      unless ex_port
    ex_up_code      = ex_up_code.to_s   unless ex_up_code
    ex_down_code    = ex_down_code.to_s unless ex_down_code

    # gen_auto_method     # auto generate class method for interface
    # draw = Tdl.inst + Tdl.draw

    instance_draw_str = instance_draw       # It must run before vars_define_inst,because some signals define when inst
    vars_exec_inst_str = vars_exec_inst     # It must run before vars_define_inst,because some signals define when vars exec

    post_str = post_inst_stack_call()

    unless post_str.strip.empty?
        post_str = pagination("ROOT REF") + post_str
    end

    draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str

    unless ex_up_code.empty?
        ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n"
    end

    unless ex_down_code.empty?
        ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n"
    end

    # str = module_head+"module #{@module_name}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + gen_lite_str() + draw + ex_down_code + "\nendmodule\n"
    # unless GlobalParam.sim
        module_name_str = @module_name
    # else
    #     module_name_str = @module_name+"_sim"
    # end
    unless head_import_packages
        str = module_head+"module #{module_name_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths
    else
        head_import_pkgs_str = head_import_packages.map{|e| "import #{e}::*;" }.join('')
        str = module_head+"module #{module_name_str} #{head_import_pkgs_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths
    end

    create_vivado_tcl if @create_tcl
    create_constraints_file if @create_sdc

    return str
end

#call_instance(name) ⇒ Object 



558
559
560
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 558

def call_instance(name)
    method(name).call
end

#CASE(cond, &block) ⇒ Object 



286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
 
# File 'lib/tdl/class_hdl/hdl_block_ifelse.rb', line 286

def CASE(cond,&block)
    new_op = ClassHDL::BlockCASE.new
    # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
    #     new_op.slaver = true
    # end
    ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
        if cond.is_a? ClassHDL::OpertorChain
            cond.slaver = true
        end
        ab.cond = cond
        block.call

    end
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
    return new_op
end

#CASEX(cond, &block) ⇒ Object 



303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
 
# File 'lib/tdl/class_hdl/hdl_block_ifelse.rb', line 303

def CASEX(cond,&block)
    new_op = ClassHDL::BlockCASEX.new
    # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
    #     new_op.slaver = true
    # end
    ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
        if cond.is_a? ClassHDL::OpertorChain
            cond.slaver = true
        end
        ab.cond = cond
        block.call

    end
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
    return new_op
end

#children_inst_tree(collect = [], &block) ⇒ Object

子 [self,[C0, [C1,] C3]]



607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 607

def children_inst_tree(collect=[],&block)
    rels = []
    # parent_rels = []
    @sub_instanced.each do |sm|
        dc = collect.dup
        if sm.origin.instance_and_children_module.empty? 
            dc << sm
            rels << dc
            yield dc if block_given?
        else 
            dc << sm
            sm.origin.children_inst_tree(dc,&block)
        end
    end
    rels 
end

#Clock(name, freqM: 100, port: :input, pin: [], iostd: [], dsize: 1, pin_prop: nil) ⇒ Object 



150
151
152
153
154
155
156
157
158
159
160
161
162
 
# File 'lib/tdl/sdlmodule/sdlmodule_port_define.rb', line 150

def Clock(name,freqM:100,port: :input,pin:[],iostd:[],dsize:1,pin_prop:nil)
    port_name_chk(name)
    pin,iostd = parse_pin_prop(pin_prop) if pin_prop
    a = Clock.new(name:name,freqM:freqM,port:port,dsize:dsize)
    add_to_new_module("@port_clocks",a)

    if block_given?
        yield(a)
    end
    # define_method(name) do
    add_method_to_itgt(name,a)
    a
end

#clog2(arg) ⇒ Object 



379
380
381
382
 
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 379

def clog2(arg)
    str = "$clog2(#{arg.to_s})"
    TdlSpace::ArrayChain.new(str)
end

#CommonCFGReg ⇒ Object 



109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
 
# File 'lib/tdl/elements/common_configure_reg.rb', line 109

def CommonCFGReg
    unless @Def_CommonCFGReg
        @Def_CommonCFGReg = InfPort.new(self,CommonCFGReg)
        class << @Def_CommonCFGReg

            def Def_CommonCFGReg_port_(name,dsize:8,asize:8,port: :master,dimension:[])
                port_name_chk(name)
                a = CommonCFGReg.new(name:name,dsize:dsize,asize:asize,port:port.to_s,dimension:dimension)
                sdlmodule.add_to_new_module("@port_datainf_c_s",a)
                if block_given?
                    yield(a)
                end
                StringBandItegration.add_method_to_itgt(name,a)
                a
            end
        end
        [:master,:slaver].each do |ty|
            @Def_CommonCFGReg.define_singleton_method(ty) do |name,dsize:8,asize: 8,dimension:[]|
                Def_CommonCFGReg_port_(name,dsize:dsize,asize: asize,port:ty,dimension:dimension)
            end
        end
        @Def_CommonCFGReg
    else
        @Def_CommonCFGReg
    end
end

#debugLogic ⇒ Object 



305
306
307
 
# File 'lib/tdl/sdlmodule/sdlmodule_arraychain.rb', line 305

def debugLogic
    TdlSpace::DefDebugLogicArrayChain.new(self)
end

#Def ⇒ Object 



122
123
124
 
# File 'lib/tdl/sdlmodule/sdlmodule_varible.rb', line 122

def Def
    @_defxp_ ||= DefXp.new(self)
end

#def_struct(&block) ⇒ Object 



195
196
197
 
# File 'lib/tdl/class_hdl/hdl_struct.rb', line 195

def def_struct(&block)
    return ClassHDL::DefStruct.new(self,block)
end

#DEFAULT(&block) ⇒ Object 



335
336
337
338
339
340
341
342
343
 
# File 'lib/tdl/class_hdl/hdl_block_ifelse.rb', line 335

def DEFAULT(&block)
    new_op = ClassHDL::BlockCASEDEFAULT.new

    ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
        block.call
    end
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
    return new_op
end

#define_ele(name, obj = nil) ⇒ Object

private



268
269
270
271
272
273
274
275
276
277
278
279
280
281
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 268

def define_ele(name,obj=nil)
    if name.is_a? BaseElm
        obj = name
        name = obj.name
    end
    name = name.to_s
    NameSpaceAdd(name)
    self.define_singleton_method(name) do |&block|
        if block_given?
            yield obj
        end
        obj
    end
end

#ELSE(&block) ⇒ Object 



274
275
276
277
278
279
280
281
282
283
284
 
# File 'lib/tdl/class_hdl/hdl_block_ifelse.rb', line 274

def ELSE(&block)
    new_op = ClassHDL::BlockELSE.new
    # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
    #     new_op.slaver = true
    # end
    ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
        block.call
    end
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
    return new_op
end

#ELSIF(cond, &block) ⇒ Object 



257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
 
# File 'lib/tdl/class_hdl/hdl_block_ifelse.rb', line 257

def ELSIF(cond,&block)
    new_op = ClassHDL::BlockELSIF.new
    # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
    #     new_op.slaver = true
    # end
    ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
        if cond.is_a? ClassHDL::OpertorChain
            cond.slaver = true
        end
        ab.cond = cond
        block.call

    end
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
    return new_op
end

#enum(*args) ⇒ Object

定义状态机



346
347
348
 
# File 'lib/tdl/class_hdl/hdl_block_ifelse.rb', line 346

def enum(*args)
    return ClassHDL::EnumStruct.new(self,*args)
end

#FOR(var: nil, start: 0, stop: 8, step: 1, &block) ⇒ Object 



80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
 
# File 'lib/tdl/class_hdl/hdl_foreach.rb', line 80

def FOR(var: nil, start: 0, stop: 8, step: 1,&block)
    ClassHDL::AssignDefOpertor.with_normal_opertor do 
        @@__for_index_cnt__ += 1
    end
    new_op = ClassHDL::BlockFOR.new

    ClassHDL::AssignDefOpertor.with_new_opertor do 
        ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
            # if cond.is_a? ClassHDL::OpertorChain
            #     cond.slaver = true
            # end
            # ab.cond = cond
            ab.var = var
            ab.start = start 
            ab.stop = stop 
            ab.step = step
            ab.flag = var || "gvar_cc_#{@@__for_index_cnt__}".to_nq
            block.call(ab.flag)

        end
    end 

    if ClassHDL::AssignDefOpertor.curr_assign_block.is_a?(ClassHDL::GenerateBlock)
        new_op.var_type = "genvar"
    else
        new_op.var_type = "integer"
    end

    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
    ClassHDL::AssignDefOpertor.with_normal_opertor do 
        @@__for_index_cnt__ -= 1
    end
    return new_op
end

#FOREACH(cond, &block) ⇒ Object 



54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
 
# File 'lib/tdl/class_hdl/hdl_foreach.rb', line 54

def FOREACH(cond,&block)
    ClassHDL::AssignDefOpertor.with_normal_opertor do 
        @@__foreach_index_cnt__ += 1
    end
    new_op = ClassHDL::BlockFOREACH.new

    ClassHDL::AssignDefOpertor.with_new_opertor do 
        ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
            if cond.is_a? ClassHDL::OpertorChain
                cond.slaver = true
            end
            ab.cond = cond
            ab.flag = "i#{@@__foreach_index_cnt__}".to_nq
            block.call(ab.flag)

        end
    end 
    
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
    ClassHDL::AssignDefOpertor.with_normal_opertor do 
        @@__foreach_index_cnt__ -= 1
    end
    return new_op
end

#function(return_type = nil) ⇒ Object

def _core_function(name,*argvs,&block)

ClassHDL::Function(self,name,*argvs,&block)

end



271
272
273
274
275
 
# File 'lib/tdl/class_hdl/hdl_function.rb', line 271

def function(return_type=nil)
    ClassHDL.disable_SdlModule_port
    ClassHDL.new_def_SdlModule_port
    return ClassHDL::DefFunction.new(self,return_type)
end

#gen_sv_module ⇒ Object 



48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
 
# File 'lib/tdl/sdlmodule/sdlmodule_draw.rb', line 48

def gen_sv_module
    # @out_sv_path ||= File.dirname(File.expand_path(__FILE__))
    return if (@origin_sv || @dont_gen_sv)
    pre_inst_stack_call
    @out_sv_path ||= '..\..\tdl\test_sdlmodule'
    # unless GlobalParam.sim
        File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
            f.puts build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
        end
    # else
    #     Tdl.Puts "+INFO+ It generate SIM top File"
    #     File.open(File.join(out_sv_path,"#{module_name}_sim.sv"),"w") do |f|
    #         f.puts build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
    #     end
    # end
end

#gen_sv_module_text ⇒ Object 



65
66
67
68
69
70
71
72
73
74
 
# File 'lib/tdl/sdlmodule/sdlmodule_draw.rb', line 65

def gen_sv_module_text
    # @out_sv_path ||= File.dirname(File.expand_path(__FILE__))
    return if (@origin_sv || @dont_gen_sv)
    pre_inst_stack_call
    @out_sv_path ||= '..\..\tdl\test_sdlmodule'
    # unless GlobalParam.sim

    return build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)

end

#generate(*args, &block) ⇒ Object 



143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
 
# File 'lib/tdl/class_hdl/hdl_generate.rb', line 143

def generate(*args,&block)
    head_str = ""
    index = 0
    @__generate_blocks__ ||= []
    tmp_sm = ClassHDL::GenerateBlock.new(self)
    kk_args = []
    @__generate_blocks__ << tmp_sm
    tmp_sm.block_index = @__generate_blocks__.size

    tmp_sm.module_name = "generate_block_#{tmp_sm.block_index}"
    if args.empty? 
        inst_obj = tmp_sm.instanced("genblk#{tmp_sm.block_index}",tmp_sm)
    else 
        inst_obj = tmp_sm.instanced("genblk#{tmp_sm.block_index}[0]",tmp_sm) ## 只取第一个
    end
    inst_obj.belong_to_module = tmp_sm

    add_children_modules(inst_obj:inst_obj ,module_poit: tmp_sm)

    args.each_index do |e|
        new_op = ClassHDL::OpertorChain.new 
        new_op.tree.push(["KK#{e}".to_nq])
        kk_args << new_op
    end
    ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAssignGenerateBlock.new ) do 
        ClassHDL::AssignDefOpertor.with_rollback_opertors(:new) do 
            tmp_sm.instance_exec(*kk_args,&block)
        end
    end

    str = (tmp_sm.instance_draw + tmp_sm.vars_exec_inst)

    gstr = generate_block_inst_iterate(str,args)
    head_str = "generate\n"
    end_str  = "endgenerate\n"
    self.Logic_inst << head_str+gstr+end_str
end

#genvar ⇒ Object 



309
310
311
 
# File 'lib/tdl/sdlmodule/sdlmodule_arraychain.rb', line 309

def genvar 
    TdlSpace::DefGenVar.new(self)
end

#has_inward_inst?(name) ⇒ Boolean

Returns:

  • (Boolean) 


38
39
40
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 38

def has_inward_inst?(name)
    @_add_to_new_module_vars.include? name.to_s
end

#has_signal?(name) ⇒ Boolean

Returns:

  • (Boolean) 


34
35
36
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 34

def has_signal?(name)
    @_add_to_new_module_vars.include? name.to_s
end

#IF(cond, &block) ⇒ Object 



240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
 
# File 'lib/tdl/class_hdl/hdl_block_ifelse.rb', line 240

def IF(cond,&block)
    new_op = ClassHDL::BlockIF.new
    # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
    #     new_op.slaver = true
    # end
    ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
        if cond.is_a? ClassHDL::OpertorChain
            cond.slaver = true
        end
        ab.cond = cond
        block.call

    end
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
    return new_op
end

#implicit_inst_module_method_missing(method, *args, &block) ⇒ Object

例化模块 @@_method_missing_sub_methds ||= [] @@_method_missing_sub_methds << ‘implicit_inst_module_method_missing’



111
112
113
114
115
116
117
118
119
120
121
122
123
 
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 111

def implicit_inst_module_method_missing(method,*args,&block)
    unless $__sdl_curr_self__.respond_to?(method)
        # super 
        ##打通 ITGT 和 module 的方法调用
        if $_implicit_curr_itgt_.slast && $_implicit_curr_itgt_.slast.respond_to?(method)
            return $_implicit_curr_itgt_.slast.send(method,*args)
        else 
            return false 
        end
    end
  
    return ClassHDL::ImplicitInstModule.new(method,self)
end

#initial(block_name = nil, &block) ⇒ Object 



73
74
75
 
# File 'lib/tdl/class_hdl/hdl_initial.rb', line 73

def initial(block_name=nil,&block)
    ClassHDL::Initial(self,block_name,&block)
end

#Initial(block_name = nil, &block) ⇒ Object 



69
70
71
 
# File 'lib/tdl/class_hdl/hdl_initial.rb', line 69

def Initial(block_name=nil,&block)
    ClassHDL::Initial(self,block_name,&block)
end

#initial_exec(str) ⇒ Object Also known as: always_sim_exec 



142
143
144
 
# File 'lib/tdl/class_hdl/hdl_initial.rb', line 142

def initial_exec(str)
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([str.to_s.to_nq]))
end

#Inout(name, dsize: 1, dimension: [], pin: [], iostd: [], pin_prop: nil) ⇒ Object 



124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
 
# File 'lib/tdl/sdlmodule/sdlmodule_port_define.rb', line 124

def Inout(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
    port_name_chk(name)
    pin,iostd = parse_pin_prop(pin_prop) if pin_prop
    # RedefOpertor.with_normal_operators do
    #     tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' )
    #     add_to_new_module("@port_logics",tmp)

    #     if block_given?
    #         yield(tmp)
    #     end
    #     # define_method(name) do
    #     add_method_to_itgt(name,tmp)
    #     tmp
    # end
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
        tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' )
        add_to_new_module("@port_logics",tmp)

        if block_given?
            yield(tmp)
        end
        add_method_to_itgt(name,tmp)
        tmp
    end
end

#inout(args = {}) ⇒ Object 



356
357
358
 
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 356

def inout(args={})
    return ClassHDL::ImplicitPortInout.new(self,args)
end

#Input(name, dsize: 1, dimension: [], pin: [], iostd: [], pin_prop: nil) ⇒ Object 



80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
 
# File 'lib/tdl/sdlmodule/sdlmodule_port_define.rb', line 80

def Input(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
    port_name_chk(name)
    pin,iostd = parse_pin_prop(pin_prop) if pin_prop
    # RedefOpertor.with_normal_operators do
    #     tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension)
    #     add_to_new_module("@port_logics",tmp)
    #     add_method_to_itgt(name,tmp)
    #     tmp
    # end
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
        tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension)
        add_to_new_module("@port_logics",tmp)
        add_method_to_itgt(name,tmp)
        tmp
    end
end

#input(args = {}) ⇒ Object

例化 input output



348
349
350
 
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 348

def input(args={})
    return ClassHDL::ImplicitPortInput.new(self,args)
end

#Instance(sdlmodule_name, name) ⇒ Object 



495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 495

def Instance(sdlmodule_name,name)
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
        name = name.to_s
        unless name.to_s =~ /^[a-zA-Z]([a-zA-Z0-9]|_)*[a-zA-Z0-9]$/
            raise TdlError.new("SdlModule Instance name ERROR: `#{name}`")
        end

        sdlmodule = SdlModule.call_module(sdlmodule_name)

        if self.module_name.eql? sdlmodule.module_name
            raise TdlError.new("SdlModule [#{@module_name}]cant instance itself ")
        end
        inst_obj = sdlmodule.instanced(name,self)
        inst_obj.belong_to_module = self
        add_children_modules(inst_obj: inst_obj,module_poit:sdlmodule)
        define_ele(name,inst_obj)
        @sub_instanced << inst_obj
        if block_given?
            yield inst_obj,self
        end
        inst_obj
    end
end

#instance_draw ⇒ Object

private



537
538
539
540
541
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 537

def instance_draw
    @sub_instanced.map do |e|
        e.inst_draw
    end.join("\n")
end

#instanced(name, parent_module) ⇒ Object 



443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 443

def instanced(name,parent_module)
    @ports ||= Hash.new
    # [@port_clocks , @port_resets , @port_logics , @port_datainfs , @port_datainf_c_s , @port_videoinfs , @port_axisinfs , @port_axi4infs , @port_axilinfs].each do |e|
    #     @ports = @ports.merge e
    # end
    # @ports = (@port_clocks + @port_resets + @port_logics + @port_datainfs + @port_datainf_c_s + @port_videoinfs + @port_axisinfs + @port_axi4infs + @port_axilinfs)
    @instance_cnt ||= 0
    inst_p = SdlInst.new(origin:self,name:name)

    @port_params.each do |k,v|
        inst_p.inst_param_hash[k.to_s] = nil
    end

    @ports.each do |k,v|
        inst_p.inner_port_hash[k.to_s] = v
        if v.is_a? SignalElm
            dele = DefaultProc.new do
                new_ele = v.copy(belong_to_module:parent_module)
                # new_ele.belong_to_module = parent_module
                new_ele.name = "#{name}_#{v.name}"
                new_ele
            end
        else
            dele = NqString.new("")
        end
        inst_p.inst_port_hash[k.to_s] = dele
    end

    @instance_cnt += 1

    inst_p
end

#inward_inst(name) ⇒ Object 



30
31
32
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 30

def inward_inst(name)
    method(name).call
end

#Itgt_Instance(sdlmodule_name, stringbanditegration, &block) ⇒ Object 



519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 519

def Itgt_Instance(sdlmodule_name,stringbanditegration,&block)
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
        unless stringbanditegration.is_a? StringBandItegration
            raise TdlError.new("Itgt_Instance is just used for StringBandItegration")
        end

        _inst_obj = Instance(sdlmodule_name,stringbanditegration.to_s,&block)

        # stringbanditegration.itgt.define_singleton_method(stringbanditegration.origin_str) do
        #     _inst_obj
        # end
        StringBandItegration.add_method_to_itgt(stringbanditegration,_inst_obj)
        _inst_obj
    end
end

#localparam ⇒ Object 



59
60
61
62
63
 
# File 'lib/tdl/class_hdl/hdl_parameter.rb', line 59

def localparam
    a = HDLClass::ImplicitInstParam.new(self)
    a.local = true
    return a
end

#logic ⇒ Object 



301
302
303
 
# File 'lib/tdl/sdlmodule/sdlmodule_arraychain.rb', line 301

def logic 
    TdlSpace::DefLogicArrayChain.new(self)
end

#logic_bind_(*args) ⇒ Object 



374
375
376
377
 
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 374

def logic_bind_(*args)
    str = "{#{args.map{|e| e.to_s }.join(',')}}"
    TdlSpace::ArrayChain.new(str)
end

#macro_add_vcs ⇒ Object 



279
280
281
282
283
 
# File 'lib/tdl/sdlmodule/sdlmodule_draw.rb', line 279

def macro_add_vcs
    @_head_macro_ ||=[]

    @_head_macro_ << "`include \"define_macro.sv\" "
end

#macro_def ⇒ Object 



273
274
275
276
277
 
# File 'lib/tdl/sdlmodule/sdlmodule_draw.rb', line 273

def macro_def
    @_head_macro_ ||=[]
    @_head_macro_ << "`timescale 1ns/1ps"
    @_head_macro_.reverse.join("\n")
end

#NameSpaceAdd(name) ⇒ Object

Raises:



283
284
285
286
287
288
289
290
291
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 283

def NameSpaceAdd(name)

    # @_add_to_new_module_vars ||= methods.map { |e| e.to_s }
    @_add_to_new_module_vars ||= []
    @_base_methods ||=  methods.map { |e| e.to_s }
    raise TdlError.new(" SdlModule[#{@module_name}] add signal error: same port or instance `#{name}` ") if (@_add_to_new_module_vars | @_base_methods ).include? name

    @_add_to_new_module_vars << name
end

#negedge(origin = nil) ⇒ Object 



140
141
142
143
144
 
# File 'lib/tdl/class_hdl/hdl_always_ff.rb', line 140

def negedge(origin=nil)
    rel = ClassHDL::ClassNegedge.new(self)
    rel.origin = origin
    return rel
end

#output(args = {}) ⇒ Object 



352
353
354
 
# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 352

def output(args={})
    return ClassHDL::ImplicitPortOutput.new(self,args)
end

#Output(name, dsize: 1, dimension: [], pin: [], iostd: [], pin_prop: nil) ⇒ Object 



97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
 
# File 'lib/tdl/sdlmodule/sdlmodule_port_define.rb', line 97

def Output(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
    port_name_chk(name)
    pin,iostd = parse_pin_prop(pin_prop) if pin_prop
    # RedefOpertor.with_normal_operators do
    #     tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic')
    #     add_to_new_module("@port_logics",tmp)

    #     if block_given?
    #         yield(tmp)
    #     end
    #     # define_method(name) do
    #     add_method_to_itgt(name,tmp)
    #     tmp
    # end
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
        tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic')
        add_to_new_module("@port_logics",tmp)

        if block_given?
            yield(tmp)
        end
        # define_method(name) do
        add_method_to_itgt(name,tmp)
        tmp
    end
end

#parameter ⇒ Object Also known as: param 



53
54
55
 
# File 'lib/tdl/class_hdl/hdl_parameter.rb', line 53

def parameter 
    return HDLClass::ImplicitInstParam.new(self)
end

#Parameter(name = :NAME, value = 0, type: nil, show: true) ⇒ Object 



62
63
64
65
66
67
68
69
70
71
72
 
# File 'lib/tdl/sdlmodule/sdlmodule_port_define.rb', line 62

def Parameter(name=:NAME,value=0,type:nil,show:true)
# def Parameter(name=:NAME,value=0,type=nil,show=true)
    port_name_chk(name)
    if value.is_a? Float
        type = :real
    end
    tmp = Parameter.new(name:name.to_s,value:value,port:true,type:type,show:show)
    add_to_new_module("@port_params",tmp)
    add_method_to_itgt(name,tmp)
    tmp
end

#Parameters(phash) ⇒ Object 



74
75
76
77
78
 
# File 'lib/tdl/sdlmodule/sdlmodule_port_define.rb', line 74

def Parameters(phash)
    phash.each do |key,value|
        Parameter(name=key,value=value,type=nil)
    end
end

#parents_inst_tree(collect = [], &block) ⇒ Object

获取模块的树状结构 父 [self,[ [P0,inst-name], [P1,] [P3, inst-name]] ]



568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
 
# File 'lib/tdl/sdlmodule/sdlmodule_instance.rb', line 568

def parents_inst_tree(collect=[],&block)
    rels = []
    # parent_rels = []
    @instanced_and_parent_module.each do |k,v|
        # ## 获取generate tree 
        # if v.is_a? ClassHDL::GenerateBlock
        #     dc = collect.dup
        #     dc << v 
        #     dc << v.belong_to_module
        #     v.parents_inst_tree(dc,&block)
        # elsif v.is_a? ClassHDL::ClearGenerateSlaverBlock
        #     dc = collect.dup
        #     dc << v.belong_to_module
        #     dc << v.belong_to_module.belong_to_module
        #     v.parents_inst_tree(dc,&block)
        # end

        # v.instance_variable_get("@sub_instanced").each do |sm|
        v.instance_and_children_module.each do |ck,cv|
            sm = ck
            dc = collect.dup
            if sm.origin == self 
                # rels << sm
                if v.instanced_and_parent_module.empty? 
                    dc << sm 
                    dc << v
                    rels << dc
                    yield dc if block_given?
                else
                    dc << sm unless cv.is_a?(ClassHDL::ClearGenerateSlaverBlock)
                    v.parents_inst_tree(dc,&block)
                end
            end
        end
    end
    rels 
end

#port ⇒ Object

端口定义



225
226
227
228
229
 
# File 'lib/tdl/class_hdl/hdl_ex_defarraychain.rb', line 225

def port 

    # return ClassHDL::PortDefChain.new(self)
    return TdlSpace::DefPortArrayChain.new(self)
end

#posedge(origin = nil) ⇒ Object 



134
135
136
137
138
 
# File 'lib/tdl/class_hdl/hdl_always_ff.rb', line 134

def posedge(origin=nil)
    rel = ClassHDL::ClassPosedge.new(self)
    rel.origin = origin
    return rel
end

#require_package(tdl_package_str, ex_code = true) ⇒ Object 



123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
 
# File 'lib/tdl/class_hdl/hdl_package.rb', line 123

def require_package(tdl_package_str,ex_code=true)
    # puts tdl_package
    if SdlModule.exist_module?(tdl_package_str) && SdlModule.call_module(tdl_package_str).instance_of?(ClassHDL::SdlPackage)
        tdl_package = SdlModule.call_module(tdl_package_str)
        @_import_packages_ ||= []
        @_import_packages_ << tdl_package
        if ex_code
            self.ex_up_code ||= '' 
            self.ex_up_code += "import #{tdl_package.module_name}::*;\n"
        end
    else 
        raise TdlError.new("Dont have packge #{tdl_package_str}")
    end 

    define_singleton_method(tdl_package_str) do 
        SdlModule.call_module(tdl_package_str)
    end

    ## 替换掉 package 里面 DefStruct 指向的 sdlmodule 

    metac = tdl_package.instance_variable_get("@_struct_meta_collect_") || []

    metac.each do |e|
        e.sdlm = self
    end
end

#Reset(name, port: :input, active: "low", pin: [], iostd: [], dsize: 1, pin_prop: nil) ⇒ Object 



164
165
166
167
168
169
170
171
172
 
# File 'lib/tdl/sdlmodule/sdlmodule_port_define.rb', line 164

def Reset(name,port: :input,active:"low",pin:[],iostd:[],dsize:1,pin_prop:nil)
    port_name_chk(name)
    pin,iostd = parse_pin_prop(pin_prop) if pin_prop
    a = Reset.new(name:name,active:active.to_s.downcase,port:port,dsize:dsize)
    add_to_new_module("@port_resets",a)
    # define_method(name){ a }
    add_method_to_itgt(name,a)
    a
end

#rubyOP(&block) ⇒ Object 



400
401
402
 
# File 'lib/tdl/class_hdl/hdl_redefine_opertor.rb', line 400

def rubyOP(&block)
    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old,&block )
end

#same_clock_domain(*vars) ⇒ Object 



369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 369

def same_clock_domain(*vars)
    objs = vars.map do |c|
        ## interface 
        if c.respond_to?(:clock) && c.clock.respond_to?(:freqM)
            c.clock.freqM 
        ## Clock
        elsif c.is_a?(Clock)
            c.freqM  
        else 
        ## other 
            nil
        end 
    end.uniq.compact

    if objs.size > 1
        raise TdlError.new " dont same clock domain"
    end

    ## verification in HDL
    objs_clks = vars.map do |c| 
        ## interface 
        if c.respond_to?(:clock)
            if c.dimension && c.dimension.any?
                c.clock
            else 
                c.clock
            end
        ## Clock
        elsif c.is_a?(Clock)
            c  
        else 
        ## other 
            c
        end 
    end

    Clock.same_clock(self, *objs_clks)
end

#show_ports ⇒ Object 



295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 295

def show_ports
    puts pagination("clock")
    hash_show @port_clocks
    puts pagination("reset")
    hash_show @port_resets
    puts pagination("parameter")
    hash_show @port_params
    puts pagination("logic")
    hash_show @port_logics
    puts pagination("datainf")
    hash_show @port_datainfs
    puts pagination("datainf_c")
    hash_show @port_datainf_c_s
    puts pagination("videoinf")
    hash_show @port_videoinfs
    puts pagination("axistream")
    hash_show @port_axisinfs
    puts pagination("axi4")
    hash_show @port_axi4infs
    puts pagination("axilite")
    hash_show @port_axilinfs
end

#signal(name) ⇒ Object 



26
27
28
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 26

def signal(name)
    method(name).call
end

#StateMachine(name, clock: nil, reset: nil, &block) ⇒ Object 



157
158
159
 
# File 'lib/tdl/sdlmodule/sdlmodule_varible.rb', line 157

def StateMachine(name,clock: nil,reset: nil, &block)
    MainStateMachine(name,:clock => clock,:reset => reset,:belong_to_module => self,&block)
end

#top_module_ref? ⇒ Boolean

Returns:

  • (Boolean) 


506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
 
# File 'lib/tdl/sdlmodule/top_module.rb', line 506

def top_module_ref?
    if self == TopModule.current.techbench 
        return true
    end
    instanced_and_parent_module.values.each do |pm|
        if pm.is_a?(TopModule)
            return true 
        else
            if pm.instanced_and_parent_module.any? 
                if pm.top_module_ref?
                    return true 
                end
            end
        end
    end
    return false
end

#top_tb_ref? ⇒ Boolean

Returns:

  • (Boolean) 


524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
 
# File 'lib/tdl/sdlmodule/top_module.rb', line 524

def top_tb_ref?
    if self == TopModule.current.techbench 
        return true
    end
    instanced_and_parent_module.values.each do |pm|
        if pm == TopModule.current.techbench ##pm.is_a?(TechBenchModule)
            return true 
        else
            if pm.instanced_and_parent_module.any? 
                if pm.top_tb_ref?
                    return true 
                end
            end
        end
    end
    return false
end

#TrackInf ⇒ Object 



137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
 
# File 'lib/tdl/elements/track_inf.rb', line 137

def TrackInf
    unless @Def_TrackInf
        @Def_TrackInf = InfPort.new(self,TrackInf)
        class << @Def_TrackInf

            def Def_TrackInf_port_(name,dsize:8,tsize:1,enable:"1'b1".to_nq,port: :master,dimension:[])
                port_name_chk(name)
                a = TrackInf.new(name:name,dsize:dsize,tsize:tsize,enable:enable,port:port.to_s,dimension:dimension)
                sdlmodule.add_to_new_module("@port_datainf_c_s",a)
                if block_given?
                    yield(a)
                end
                StringBandItegration.add_method_to_itgt(name,a)
                a
            end
        end
        [:master,:slaver].each do |ty|
            @Def_TrackInf.define_singleton_method(ty) do |name,dsize:8,tsize: 1,enable:"1'b1".to_nq,dimension:[]|
                Def_TrackInf_port_(name,dsize:dsize,tsize: tsize,enable:enable,port:ty,dimension:dimension)
            end
        end
        @Def_TrackInf
    else
        @Def_TrackInf
    end
end

#try_call_ele(name) ⇒ Object 



107
108
109
110
111
112
113
114
 
# File 'lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb', line 107

def try_call_ele(name)
    # puts SdlModule.allmodule_name
    if @_add_to_new_module_vars.include?(name.to_s)
        method(name).call
    else
        nil
    end
end

#TryDef ⇒ Object 



116
117
118
 
# File 'lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb', line 116

def TryDef
    @_trydefxp_ ||= TryDefXp.new(self)
end

#urandom_range(a, b) ⇒ Object 



16
17
18
 
# File 'lib/tdl/class_hdl/hdl_random.rb', line 16

def urandom_range(a,b)
    return "$urandom_range(#{a},#{b})".to_nq
end

#var_common(a, &block) ⇒ Object 



126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
 
# File 'lib/tdl/sdlmodule/sdlmodule_varible.rb', line 126

def var_common(a,&block)
    class_v = a.class
    unless self.instance_variable_get("@#{class_v}_collect")
        self.instance_variable_set("@#{class_v}_collect",[])
    end

    unless self.instance_variable_get("@#{class_v}_id")
        self.instance_variable_set("@#{class_v}_id",1)
    end

    a.id = self.instance_variable_get("@#{class_v}_id")
    self.instance_variable_set("@#{class_v}_id",a.id+1)

    a.belong_to_module = self

    self.instance_variable_get("@#{class_v}_collect") << a

    define_ele(a)

    if block_given?
        yield(a)
    end

    a
end

#vars_define_inst ⇒ Object 



216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 216

def vars_define_inst
    vars = []
    @@ele_array.each do |e|
        head_str = "@#{e.to_s}"
        vars += self.instance_variable_get("#{head_str}_collect")
    end

    ele_str = []
    (self.instance_variable_get("@__element_collect__") || [] ).each do |e|
        rel = e._inner_inst
        if rel 
            ele_str << rel 
        end
    end

    vars_inst = vars.map{ |v| v.inst }

    var_str = vars_inst.join("\n")
    var_str +"\n"+ ele_str.join("\n")
end

#vars_exec_inst ⇒ Object 



238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
 
# File 'lib/tdl/sdlmodule/sdlmodule.rb', line 238

def vars_exec_inst
    vars_inst = []
    vars_draw = []

    @@ele_array.each do |e|
        head_str = "@#{e.to_s}"
        vars_inst |= self.instance_variable_get("#{head_str}_inst")
        vars_draw |= self.instance_variable_get("#{head_str}_draw")
    end

    vars_inst_str = vars_inst.map do |e|
        if e.is_a? String
            e
        elsif e.is_a? Proc
            e.call
        end
    end.join("\n")

    vars_draw_str = vars_draw.map do |e|
        if e.is_a? String
            e
        elsif e.is_a? Proc
            e.call
        end
    end.join("\n")


    vars_inst_str + vars_draw_str
end

#vcs_string(total = 64, local = false) ⇒ Object 



65
66
67
68
69
70
71
 
# File 'lib/tdl/class_hdl/hdl_parameter.rb', line 65

def vcs_string(total=64,local=false)
    a = HDLClass::ImplicitInstParam.new(self)
    self.macro_add_vcs
    a.vcs_string = total
    a.local = local
    return a
end

#verify ⇒ Object 



133
134
135
 
# File 'lib/tdl/class_hdl/hdl_verify.rb', line 133

def verify
    vinst = ClassHDL::Verify.new(self)
end

#WHEN(*cond, &block) ⇒ Object 



320
321
322
323
324
325
326
327
328
329
330
331
332
333
 
# File 'lib/tdl/class_hdl/hdl_block_ifelse.rb', line 320

def WHEN(*cond,&block)
    new_op = ClassHDL::BlockCASEWHEN.new

    ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
        if cond.is_a? ClassHDL::OpertorChain
            cond.slaver = true
        end
        ab.cond = cond
        block.call

    end
    ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
    return new_op
end