Class: ConstraintsVerb

Inherits:
Object
  • Object
show all
Defined in:
lib/tdl/exlib/constraints_verb.rb

Instance Method Summary collapse

Constructor Details

#initialize ⇒ ConstraintsVerb

Returns a new instance of ConstraintsVerb.



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# File 'lib/tdl/exlib/constraints_verb.rb', line 4

def initialize
    @package_pin_and_IOSTANDARD ||= []
    @clock_xds ||=[]
    @ex_constraints = ""
    @hash_const ||= Hash.new
    @hash_bitstream_const ||= Hash.new
    @pins_used ||=[]
end

Instance Method Details

#add(*names) ⇒ Object 



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# File 'lib/tdl/exlib/constraints_verb.rb', line 151

def add(*names)
    names.each do |e|
        sadd(e)
    end
end

#add_const(*strs) ⇒ Object 



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# File 'lib/tdl/exlib/constraints_verb.rb', line 145

def add_const(*strs)
    strs.each do |str|
        @ex_constraints  += (str+"\n")
    end
end

#add_property(port_name, pin_name, iostandard, pulltype = nil, drive = nil) ⇒ Object

Raises:



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# File 'lib/tdl/exlib/constraints_verb.rb', line 13

def add_property(port_name,pin_name,iostandard,pulltype=nil,drive=nil)
    if pin_name.respond_to?("empty?") && pin_name.empty?
        pin_name = ""
    end

    if iostandard.respond_to?("empty?") && iostandard.empty?
        iostandard = ""
    end

    if pin_name.empty? && iostandard.empty?
        return
    end

    @clock_xds << port_name if (port_name.is_a? Clock)

    raise TdlError.new("\nConstraints port_name[#{port_name.to_s}] is'nt a SignalElm\n" ) unless port_name.is_a? SignalElm
    unless port_name.respond_to?(:dsize) && port_name.dsize != 1
        # raise TdlError.new("\nConstraints pin_name is a Array\n" ) if pin_name.is_a? Array
        # raise TdlError.new("\nConstraints iostandard is a Array\n" ) if iostandard.is_a? Array
        # @@clock_xds << port_name if (port_name.is_a? Clock) && (port_name.freqM.is_a? Numeric)
        pin_name = pin_name[0] if pin_name.is_a? Array
        @package_pin_and_IOSTANDARD << [port_name.signal,pin_name.to_s.upcase,iostandard.to_s.upcase,pulltype,drive.to_s]
        if @pins_used.include? pin_name.to_s.upcase
            raise TdlError.new("\nConstraints: PORT[#{port_name.signal}]@PIN[#{pin_name.to_s.upcase}] is fault,because #{pin_name.to_s.upcase} has be used\n")
        end
        @pins_used << pin_name.to_s.upcase
    else
        iostandard = ([iostandard] * pin_name.size ) unless iostandard.is_a? Array
        pulltype = ([pulltype] * pin_name.size ) unless pulltype.is_a? Array
        drive = ([drive] * pin_name.size ) unless drive.is_a? Array

        pin_name = ((pin_name.is_a?(Array) && pin_name) || [pin_name] )
        pin_name.each_index do |index|
            @package_pin_and_IOSTANDARD << [port_name[index],pin_name[index].to_s.upcase,iostandard[index].to_s.upcase,pulltype[index].to_s,drive[index].to_s]

            if @pins_used.include?  pin_name[index].to_s.upcase
                raise TdlError.new("\nConstraints: PORT[#{port_name[index]}]@PIN[#{ pin_name[index].to_s.upcase}] is fault,because #{ pin_name[index].to_s.upcase} has be used\n")
            end
            @pins_used << pin_name[index].to_s.upcase
        end
    end
end

#clockProperties ⇒ Object 



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# File 'lib/tdl/exlib/constraints_verb.rb', line 101

def clockProperties
    @@system_jitter ||= 0.1
    head_str = "##-------------------------- CLOCK SET ---------------------------------- ##\nset_system_jitter #{@@system_jitter} \n"
    end_str  = "##========================== CLOCK SET ================================== ##\n"
    str = @clock_xds.map do |c|
        prie = ((1000.0)/c.freqM).round(3)
        half_prie = ((500.0)/c.freqM).round(3)
        if c.dsize == 1
            "create_clock -period #{prie} -name #{c.signal} -waveform {0.000 #{half_prie}} [get_ports #{c.signal}]\n# set_input_jitter [get_clocks -of_objects [get_ports #{c.signal}]] #{c.jitter}\n"
        else
            sub_str = ''
            c.dsize.times do |xi|
                sub_str += "create_clock -period #{prie} -name #{c.name}_#{xi} -waveform {0.000 #{half_prie}} [get_ports #{c.signal(xi)}]\n# set_input_jitter [get_clocks -of_objects [get_ports #{c.signal(xi)}]] #{c.jitter}\n"
            end
            sub_str
        end
    end.join("")
    head_str + str + end_str
end

#constProperties ⇒ Object 



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# File 'lib/tdl/exlib/constraints_verb.rb', line 121

def constProperties
"
## -------------------------- FALSE PATH SET ---------------------------------- ##
# set_false_path -from [get_pins -hier -regexp .*cross_clk.*ltc.*] -to [all_registers]
set_max_delay -from [get_pins -hier -regexp .*cross_clk.*ltc.*] -to [all_registers] 20.00
## set_false_path -from [get_pins -hierarchical \"*cross_clk*\"] -to [all_registers]
# set_false_path -from [all_registers] -to [get_pins -hier -regexp .*cross_clk.*ltc.*]
set_max_delay -from [all_registers] -to [get_pins -hier -regexp .*cross_clk.*ltc.*] 20.00
## set_false_path -from [all_registers] -to [get_pins -hierarchical \"*cross_clk*\"]

# set_false_path -from [get_pins -hier -regexp .*xilinx_reset_sync.*reset_sync.*] -to [all_registers]
set_max_delay -from [get_pins -hier -regexp .*xilinx_reset_sync.*reset_sync.*] -to [all_registers] 40.000
## set_false_path -from [get_pins -hierarchical \"*xilinx_reset_sync*reset_sync*\"] -to [all_registers]
#{@hash_const.map{|key,value| value}.join("")}
## ========================== FALSE PATH SET =================================== ##
## -------------------------- EX SET ---------------------------------- ##
#{@ex_constraints}
## ========================== EX SET =================================== ##
## -------------------------- BITSTREAM SET ---------------------------------- ##
#{@hash_bitstream_const.map{|key,value| value}.join("")}
## ========================== BITSTREAM SET =================================== ##
"
end

#pinProperties ⇒ Object 



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# File 'lib/tdl/exlib/constraints_verb.rb', line 56

def pinProperties
    cstr = self.clockProperties
    head_str = "##-------------------------- PIN SET ---------------------------------- ##\n"
    end_str  = "##========================== PIN SET ================================== ##\n"
    pstr = @package_pin_and_IOSTANDARD.map do |ar|
        if ar[0] =~ /\[.*\]$/
            qstr = "{#{ar[0]}}"
        else
            qstr = ar[0]
        end
        unless ar[1].empty?
            str1 = "set_property PACKAGE_PIN #{ar[1]} [get_ports #{qstr}]\n"
        else
            str1 = "# #{ar[0]} dont have any PIN to be assigned\n"
        end

        if  ar[2].empty? || ar[2].to_s.empty?
            str2 = "# #{ar[0]} dont have any IOSTANDARD to be assigned\n"
        else
            str2 = "set_property IOSTANDARD #{ar[2]} [get_ports #{qstr}]\n"
        end

        if ar[3]  && !ar[3].empty?  # PULLUP PULLDOWN
            str_pullup = "set_property #{ar[3].upcase} true [get_ports #{qstr}]\n"
        else
            str_pullup = ""
        end

        if ar[4] && !ar[4].empty?
            str_drive = "set_property DRIVE #{ar[4]} [get_ports #{qstr}]\n"
        else
            str_drive = ""
        end

        str1 + str2 + str_pullup + str_drive

    end.join("")

    cstr + head_str + pstr + end_str
end

#xds ⇒ Object 



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# File 'lib/tdl/exlib/constraints_verb.rb', line 97

def xds
    pinProperties() + constProperties()
end