Class: Axi4

Inherits:
TdlSpace::TdlBaseInterface show all
Extended by:
BaseFunc
Includes:
BaseModule
Defined in:
lib/tdl/elements/axi4.rb,
lib/tdl/axi4/bak/ddr3.rb,
lib/tdl/elements/axi4.rb,
lib/tdl/elements/axi4.rb,
lib/tdl/elements/axi4.rb,
lib/tdl/elements/axi4.rb,
lib/tdl/elements/axi4.rb,
lib/tdl/elements/axi4.rb,
lib/tdl/axi4/axi4_direct.rb,
lib/tdl/rebuild_ele/axi4.rb,
lib/tdl/axi4/axi4_pipe_auto.rb,
lib/tdl/bfm/axi4_illegal_bfm.rb,
lib/tdl/axi4/axi4_direct_auto.rb,
lib/tdl/VideoInf/video_to_axi4.rb,
lib/tdl/axi4/bak/axi4_pipe_auto.rb,
lib/tdl/VideoInf/video_from_axi4.rb,
lib/tdl/axi4/axi4_direct_A1_auto.rb,
lib/tdl/axi4/axi4_pipe_verb_auto.rb,
lib/tdl/axi4/bak/axi4_direct_auto.rb,
lib/tdl/axi4/idata_pool_axi4_auto.rb,
lib/tdl/axi4/odata_pool_axi4_auto.rb,
lib/tdl/axi4/axi4_direct_verb_auto.rb,
lib/tdl/axi4/axi4_packet_fifo_auto.rb,
lib/tdl/axi4/bak/axi4_data_convert.rb,
lib/tdl/axi4/bak/axi4_partition_od.rb,
lib/tdl/axi4/axi4_interconnect_verb.rb,
lib/tdl/axi4/odata_pool_axi4_A1_auto.rb,
lib/tdl/axi_stream/bak/video_to_VDMA.rb,
lib/tdl/axi4/bak/idata_pool_axi4_auto.rb,
lib/tdl/axi4/bak/odata_pool_axi4_auto.rb,
lib/tdl/axi4/bak/axi4_direct_verb_auto.rb,
lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb,
lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb,
lib/tdl/axi4/bak/odata_pool_axi4_A1_auto.rb,
lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb,
lib/tdl/axi_stream/bak/video_to_VDMA_auto.rb,
lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb,
lib/tdl/axi_stream/bak/idata_pool_axi4_auto.rb,
lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb,
lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb,
lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb,
lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb,
lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb,
lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb

Overview

2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative ‘....tdltdl’

Direct Known Subclasses

Axi4IllegalBFM

Constant Summary collapse

BOTH = 
"BOTH"
ONLY_READ = 
"ONLY_READ"
ONLY_WRITE = 
"ONLY_WRITE"
Synth_REP =

parse text for autogen method and constant ###

Regexp.union(/\(\*\s+axi4\s*=\s*"true"\s+\*\)/,/\(\*\s+axi_inf\s*=\s*"true"\s+\*\)/)
INTERFACE_VECTOR_SIGNALS = 
%W{
    axi_awid
    axi_awaddr
    axi_awlen
    axi_arid
    axi_araddr
    axi_arlen
    axi_wdata
    axi_wstrb
    axi_rdata
    axi_rresp
    axi_rid
    axi_bid
    axi_wcnt
    axi_rcnt
}
INTERFACE_S_SIGNALS = 
%W{
    axi_aclk
    axi_aresetn
    axi_awsize
    axi_awburst
    axi_awlock
    axi_awcache
    axi_awprot
    axi_awqos
    axi_awvalid
    axi_awready
    axi_arsize
    axi_arburst
    axi_arlock
    axi_arcache
    axi_arprot
    axi_arqos
    axi_arvalid
    axi_arready
    axi_bready
    axi_bresp
    axi_bvalid
    axi_wlast
    axi_wvalid
    axi_wready
    axi_rready
    axi_rlast
    axi_rvalid
    DSIZE
    IDSIZE
    ASIZE
    ADDR_STEP
    LSIZE
    MODE
    axi_wcnt
    axi_rcnt
    FreqM
}
PORT_REP =

def initialize(name:“axi4”,clock:nil,reset:nil,dsize:8,idsize:1,asize:8,lsize:8,mode:BOTH,port:false,addr_step:1.0,dimension:[],freqM:nil,belong_to_module: nil)

super belong_to_module
self.inst_name = name 
self.clock = clock 
self.reset = reset 
self.dsize = dsize 
self.idsize = idsize
self.asize = asize 
self.lsize = lsize
self.mode = mode 
self.modport_type = port
self.addr_step = addr_step
self.dimension = dimension
self.freqM = freqM

end

/(?<up_down>\(\*\s+(?<ud_name>axi4_up|axi4_down)\s*=\s*"true"\s+\*\))?\s*(axi_inf\.)(?<modport>master|slaver|master_wr|slaver_wr|master_rd|slaver_rd|master_wr_aux|master_wr_aux_no_resp|master_rd_aux|mirror_wr|mirror_rd)\s+(?<name>\w+)\s*(?<vector>\[.*?\])?/m
UP_STREAM_REP = 
/axi4_up/

Instance Attribute Summary collapse

Attributes inherited from TdlSpace::TdlBaseInterface

#belong_to_module

Attributes included from TdlSpace::VarElemenCore

#dimension, #inst_name, #logic_type

Class Method Summary collapse

Instance Method Summary collapse

Methods included from BaseFunc

check_same, check_same_class, check_same_clock, check_same_dsize

Methods included from BaseModule

#length, #to_s

Methods inherited from TdlSpace::TdlBaseInterface

#element_to_module, #force_name_copy, inherited, #name_copy, #path_refs, subclass, #use_which_freq_when_copy

Methods included from TdlSpace::VarElemenAttr

#_io_map, #clock_io_map, #comm_io_map, #comm_io_maps_same, #gen_sv_interface, #get_class_var, #hdl_name, #modports, #param_map, #pdata_map, #reset_io_map, #sdata_maps, #set_class_var

Methods included from TdlSpace::VarElemenCore

#_inner_inst, #instance, #modport_type, #modport_type=, #to_s

Methods included from TdlSpace::ExCreateTP

#root_ref

Methods included from AxiTdl::TestUnitTrack

#tracked_by_dve

Constructor Details

#initialize(name: "axi4", clock: nil, reset: nil, dsize: 8, idsize: 1, asize: 8, lsize: 8, mode: BOTH, port: false, addr_step: 1.0, dimension: [], freqM: nil) ⇒ Axi4

def initialize(name:“axi4”,clock:nil,reset:nil,dsize:8,idsize:1,asize:8,max_len:256,mode:BOTH,port:false)



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# File 'lib/tdl/elements/axi4.rb', line 21

def initialize(name:"axi4",clock:nil,reset:nil,dsize:8,idsize:1,asize:8,lsize:8,mode:BOTH,port:false,addr_step:1.0,dimension:[],freqM:nil)
    name_legal?(name)
    super(dimension:dimension,clock:clock,reset:reset,freqM:freqM)
    @name = name
    # raise TdlError.new "\nRESET CAN'T BE NIL\n" if reset.nil?
    @dsize = dsize
    @idsize = idsize
    @asize = asize
    # @lsize = CMath.log2(max_len).to_i + ( (max_len > 2**(CMath.log2(max_len).to_i))? 1:0)
    # @max_len= max_len
    @lsize = lsize
    @mode = mode
    @port = port
    @addr_step = addr_step
    @dimension = dimension
    # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Axi4.id
    # @correlation_proc = ""
    # if @port
    #     GlobalParam.CurrTdlModule.BindEleClassVars.Axi4.ports << self
    # else
    #     GlobalParam.CurrTdlModule.BindEleClassVars.Axi4.inst_stack << method(:inst).to_proc
    # end
    # GlobalParam.CurrTdlModule.BindEleClassVars.Axi4.pre_inst_stack << method(:inter_pre_inst_stack).to_proc
    # GlobalParam.CurrTdlModule.BindEleClassVars.Axi4.draw_stack << method(:draw).to_proc
end

Instance Attribute Details

#addr_step ⇒ Object

Returns the value of attribute addr_step.



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# File 'lib/tdl/elements/axi4.rb', line 18

def addr_step
  @addr_step
end

#asize ⇒ Object

Returns the value of attribute asize.



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# File 'lib/tdl/elements/axi4.rb', line 18

def asize
  @asize
end

#dsize ⇒ Object

<tdl_key><hdl_key><default_value>



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# File 'lib/tdl/rebuild_ele/axi4.rb', line 10

def dsize
  @dsize
end

#ghost ⇒ Object

Returns the value of attribute ghost.



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# File 'lib/tdl/elements/axi4.rb', line 18

def ghost
  @ghost
end

#id ⇒ Object

Returns the value of attribute id.



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# File 'lib/tdl/elements/axi4.rb', line 18

def id
  @id
end

#idsize ⇒ Object

Returns the value of attribute idsize.



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# File 'lib/tdl/elements/axi4.rb', line 18

def idsize
  @idsize
end

#lsize ⇒ Object

Returns the value of attribute lsize.



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# File 'lib/tdl/elements/axi4.rb', line 18

def lsize
  @lsize
end

#mode ⇒ Object

Returns the value of attribute mode.



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# File 'lib/tdl/elements/axi4.rb', line 18

def mode
  @mode
end

#name ⇒ Object

Returns the value of attribute name.



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# File 'lib/tdl/elements/axi4.rb', line 18

def name
  @name
end

#port ⇒ Object

Returns the value of attribute port.



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# File 'lib/tdl/elements/axi4.rb', line 18

def port
  @port
end

Class Method Details

.axi4_combin_wr_rd_batch(wr_slaver: "wr_slaver", rd_slaver: "rd_slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb', line 60

def self.axi4_combin_wr_rd_batch(
    wr_slaver:"wr_slaver",
    rd_slaver:"rd_slaver",
    master:"master",
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [wr_slaver,rd_slaver,master].first.belong_to_module unless belong_to_module
    
    
    belong_to_module.Axi4_NC._axi4_combin_wr_rd_batch(
        wr_slaver:wr_slaver,
        rd_slaver:rd_slaver,
        master:master)
    return return_stream
end

.axi4_data_convert(up_stream: nil, down_stream: nil, dsize: 8, copy_inf: nil) ⇒ Object 



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# File 'lib/tdl/axi4/bak/axi4_data_convert.rb', line 34

def self.axi4_data_convert(up_stream:nil,down_stream:nil,dsize:8,copy_inf:nil)
    if up_stream==nil && down_stream==nil
        new_up_stream = copy_inf.copy(dsize:dsize)
        new_down_stream = copy_inf.copy(dsize:dsize)
    elsif up_stream==nil
        new_up_stream = down_stream.copy(dsize:dsize)
        new_down_stream = down_stream
    elsif down_stream==nil
        new_up_stream = up_stream
        new_down_stream = up_stream.copy(dsize:dsize)
    end

    new_down_stream.axi4_data_convert(up_stream:new_up_stream,down_stream:new_down_stream)

    if up_stream==nil && down_stream==nil
        return [new_up_stream,new_down_stream]
    elsif up_stream==nil
        return new_up_stream
    elsif down_stream==nil
        return new_down_stream
    end

end

.axi4_direct(mode: "BOTH_to_BOTH", slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_direct_auto.rb', line 60

def self.axi4_direct(
    mode:"BOTH_to_BOTH",
    slaver:"slaver",
    master:"master",
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [slaver,master].first.belong_to_module unless belong_to_module
    
    
    belong_to_module.Axi4_NC._axi4_direct(
        mode:mode,
        slaver:slaver,
        master:master)
    return return_stream
end

.axi4_direct_a1(mode: "BOTH_to_BOTH", slaver: "slaver", master: "master", up_stream: nil, down_stream: nil, belong_to_module: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_direct_A1_auto.rb', line 79

def self.axi4_direct_a1(
    mode:"BOTH_to_BOTH",
    slaver:"slaver",
    master:"master",
    up_stream:nil,
    down_stream:nil,
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [slaver,master].first.belong_to_module unless belong_to_module
    
    if down_stream.nil? && master.eql?("master")
        if up_stream.is_a? Axi4
            down_stream = up_stream.copy
        else
            down_stream = slaver.copy
        end
        return_stream = down_stream
    end

    
    if up_stream.nil? && slaver.eql?("slaver")
        if down_stream.is_a? Axi4
            up_stream = down_stream.copy
        else
            up_stream = master.copy
        end
        return_stream = up_stream
    end

    
    if down_stream.is_a? Axi4
        down_stream.axi4_direct_a1(
            mode:mode,
            slaver:slaver,
            master:master,
            up_stream:up_stream,
            down_stream:down_stream)
    elsif master.is_a? Axi4
        master.axi4_direct_a1(
            mode:mode,
            slaver:slaver,
            master:master,
            up_stream:up_stream,
            down_stream:down_stream)
    else
        belong_to_module.Axi4_NC.axi4_direct_a1(
            mode:mode,
            slaver:slaver,
            master:master,
            up_stream:up_stream,
            down_stream:down_stream)
    end
    return return_stream
end

.axi4_direct_verb(slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_direct_verb_auto.rb', line 54

def self.axi4_direct_verb(
    slaver:"slaver",
    master:"master",
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [slaver,master].first.belong_to_module unless belong_to_module
    
    
    belong_to_module.Axi4_NC._axi4_direct_verb(
        slaver:slaver,
        master:master)
    return return_stream
end

.axi4_long_to_axi4_wide(slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb', line 54

def self.axi4_long_to_axi4_wide(
    slaver:"slaver",
    master:"master",
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [slaver,master].first.belong_to_module unless belong_to_module
    
    
    belong_to_module.Axi4_NC._axi4_long_to_axi4_wide(
        slaver:slaver,
        master:master)
    return return_stream
end

.axi4_long_to_axi4_wide_a1(partition: "ON", slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb', line 60

def self.axi4_long_to_axi4_wide_a1(
    partition:"ON",
    slaver:"slaver",
    master:"master",
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [slaver,master].first.belong_to_module unless belong_to_module
    
    
    belong_to_module.Axi4_NC._axi4_long_to_axi4_wide_a1(
        partition:partition,
        slaver:slaver,
        master:master)
    return return_stream
end

.axi4_long_to_axi4_wide_verb(pipe: "OFF", partition: "ON", slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb', line 65

def self.axi4_long_to_axi4_wide_verb(
    pipe:"OFF",
    partition:"ON",
    slaver:"slaver",
    master:"master",
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [slaver,master].first.belong_to_module unless belong_to_module
    
    
    belong_to_module.Axi4_NC._axi4_long_to_axi4_wide_verb(
        pipe:pipe,
        partition:partition,
        slaver:slaver,
        master:master)
    return return_stream
end

.axi4_packet_fifo(pipe: "OFF", depth: 4, mode: "BOTH", axi_in: "axi_in", axi_out: "axi_out", up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_packet_fifo_auto.rb', line 89

def self.axi4_packet_fifo(
    pipe:"OFF",
    depth:4,
    mode:"BOTH",
    axi_in:"axi_in",
    axi_out:"axi_out",
    up_stream:nil,
    down_stream:nil,
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [axi_in,axi_out].first.belong_to_module unless belong_to_module
    
    if down_stream.nil? && axi_out.eql?("axi_out")
        if up_stream.is_a? Axi4
            down_stream = up_stream.copy
        else
            down_stream = axi_in.copy
        end
        return_stream = down_stream
    end

    
    if up_stream.nil? && axi_in.eql?("axi_in")
        if down_stream.is_a? Axi4
            up_stream = down_stream.copy
        else
            up_stream = axi_out.copy
        end
        return_stream = up_stream
    end

    
    if down_stream.is_a? Axi4
        down_stream.axi4_packet_fifo(
            pipe:pipe,
            depth:depth,
            mode:mode,
            axi_in:axi_in,
            axi_out:axi_out,
            up_stream:up_stream,
            down_stream:down_stream)
    elsif axi_out.is_a? Axi4
        axi_out.axi4_packet_fifo(
            pipe:pipe,
            depth:depth,
            mode:mode,
            axi_in:axi_in,
            axi_out:axi_out,
            up_stream:up_stream,
            down_stream:down_stream)
    else
        belong_to_module.Axi4_NC.axi4_packet_fifo(
            pipe:pipe,
            depth:depth,
            mode:mode,
            axi_in:axi_in,
            axi_out:axi_out,
            up_stream:up_stream,
            down_stream:down_stream)
    end
    return return_stream
end

.axi4_partition_od(up_stream: nil, down_stream: nil, addr_step: "1.0", copy_inf: nil, max_len: copy_inf.max_len) ⇒ Object 



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# File 'lib/tdl/axi4/bak/axi4_partition_od.rb', line 40

def self.axi4_partition_od(up_stream:nil,down_stream:nil,addr_step:"1.0",copy_inf:nil,max_len:copy_inf.max_len)
    if up_stream==nil && down_stream==nil
        new_up_stream = copy_inf.copy(max_len:max_len)
        new_down_stream = copy_inf.copy(max_len:max_len)
    elsif up_stream==nil
        new_up_stream = down_stream.copy(max_len:max_len)
        new_down_stream = down_stream
    elsif down_stream==nil
        new_up_stream = up_stream
        new_down_stream = up_stream.copy(max_len:max_len)
    end


    new_down_stream.axi4_partition_od(up_stream:new_up_stream,down_stream:new_down_stream,addr_step:addr_step)

    if up_stream==nil && down_stream==nil
        return [new_up_stream,new_down_stream]
    elsif up_stream==nil
        return new_up_stream
    elsif down_stream==nil
        return new_down_stream
    end

end

.axi4_pipe(slaver: "slaver", master: "master", up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_pipe_auto.rb', line 73

def self.axi4_pipe(
    slaver:"slaver",
    master:"master",
    up_stream:nil,
    down_stream:nil,
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [slaver,master].first.belong_to_module unless belong_to_module
    
    if down_stream.nil? && master.eql?("master")
        if up_stream.is_a? Axi4
            down_stream = up_stream.copy
        else
            down_stream = slaver.copy
        end
        return_stream = down_stream
    end

    
    if up_stream.nil? && slaver.eql?("slaver")
        if down_stream.is_a? Axi4
            up_stream = down_stream.copy
        else
            up_stream = master.copy
        end
        return_stream = up_stream
    end

    
    if down_stream.is_a? Axi4
        down_stream.axi4_pipe(
            slaver:slaver,
            master:master,
            up_stream:up_stream,
            down_stream:down_stream)
    elsif master.is_a? Axi4
        master.axi4_pipe(
            slaver:slaver,
            master:master,
            up_stream:up_stream,
            down_stream:down_stream)
    else
        belong_to_module.Axi4_NC.axi4_pipe(
            slaver:slaver,
            master:master,
            up_stream:up_stream,
            down_stream:down_stream)
    end
    return return_stream
end

.axi4_pipe_verb(slaver: "slaver", master: "master", up_stream: nil, down_stream: nil, belong_to_module: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_pipe_verb_auto.rb', line 73

def self.axi4_pipe_verb(
    slaver:"slaver",
    master:"master",
    up_stream:nil,
    down_stream:nil,
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [slaver,master].first.belong_to_module unless belong_to_module
    
    if down_stream.nil? && master.eql?("master")
        if up_stream.is_a? Axi4
            down_stream = up_stream.copy
        else
            down_stream = slaver.copy
        end
        return_stream = down_stream
    end

    
    if up_stream.nil? && slaver.eql?("slaver")
        if down_stream.is_a? Axi4
            up_stream = down_stream.copy
        else
            up_stream = master.copy
        end
        return_stream = up_stream
    end

    
    if down_stream.is_a? Axi4
        down_stream.axi4_pipe_verb(
            slaver:slaver,
            master:master,
            up_stream:up_stream,
            down_stream:down_stream)
    elsif master.is_a? Axi4
        master.axi4_pipe_verb(
            slaver:slaver,
            master:master,
            up_stream:up_stream,
            down_stream:down_stream)
    else
        belong_to_module.Axi4_NC.axi4_pipe_verb(
            slaver:slaver,
            master:master,
            up_stream:up_stream,
            down_stream:down_stream)
    end
    return return_stream
end

.axi4_to_native_for_ddr_ip_verb(addr_width: 27, data_width: 256, app_addr: "app_addr", app_cmd: "app_cmd", app_en: "app_en", app_wdf_data: "app_wdf_data", app_wdf_end: "app_wdf_end", app_wdf_mask: "app_wdf_mask", app_wdf_wren: "app_wdf_wren", app_rd_data: "app_rd_data", app_rd_data_end: "app_rd_data_end", app_rd_data_valid: "app_rd_data_valid", app_rdy: "app_rdy", app_wdf_rdy: "app_wdf_rdy", init_calib_complete: "init_calib_complete", axi_inf: "axi_inf") ⇒ Object 



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# File 'lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb', line 45

def self.axi4_to_native_for_ddr_ip_verb(addr_width:27,data_width:256,app_addr:"app_addr",app_cmd:"app_cmd",app_en:"app_en",app_wdf_data:"app_wdf_data",app_wdf_end:"app_wdf_end",app_wdf_mask:"app_wdf_mask",app_wdf_wren:"app_wdf_wren",app_rd_data:"app_rd_data",app_rd_data_end:"app_rd_data_end",app_rd_data_valid:"app_rd_data_valid",app_rdy:"app_rdy",app_wdf_rdy:"app_wdf_rdy",init_calib_complete:"init_calib_complete",axi_inf:"axi_inf")
    return_stream = nil
    
    
    NC._axi4_to_native_for_ddr_ip_verb(addr_width:addr_width,data_width:data_width,app_addr:app_addr,app_cmd:app_cmd,app_en:app_en,app_wdf_data:app_wdf_data,app_wdf_end:app_wdf_end,app_wdf_mask:app_wdf_mask,app_wdf_wren:app_wdf_wren,app_rd_data:app_rd_data,app_rd_data_end:app_rd_data_end,app_rd_data_valid:app_rd_data_valid,app_rdy:app_rdy,app_wdf_rdy:app_wdf_rdy,init_calib_complete:init_calib_complete,axi_inf:axi_inf)
    return return_stream
end

.cal_addr_step(target_dsize, origin_data) ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 531

def self.cal_addr_step(target_dsize,origin_data)
    if origin_data.is_a? Axi4
        origin_data.cal_addr_step(target_dsize)
    elsif origin_data.is_a? Hash
        raise TdlError.new("\nWhen Cal Axi4 ADDR_STEP: Hash\n[#{origin_data}]\n dont have key dsize\n")  unless( origin_data.include? :dsize)
        raise TdlError.new("\nWhen Cal Axi4 ADDR_STEP: Hash\n[#{origin_data}]\n dont have key addr_step\n")  unless( origin_data.include? :addr_step)
        with_new_align do
            NqString.new("#{align_signal(origin_data[:addr_step])}*#{align_signal(target_dsize)}/#{align_signal(origin_data[:dsize])}")
        end
    else
        raise TdlError.new("\nCant Cal Axi4 ADDR_STEP,because origin_data Type Error,it must Hash or Axi4 \n")
    end
end

.idata_pool_axi4(dsize: 8, source_addr: "source_addr", size: "size", valid: "valid", ready: "ready", last_drop: "last_drop", data: "data", empty: "empty", wr_en: "wr_en", sewage_valve: "sewage_valve", axi_master: "axi_master", down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/idata_pool_axi4_auto.rb', line 108

def self.idata_pool_axi4(
    dsize:8,
    source_addr:"source_addr",
    size:"size",
    valid:"valid",
    ready:"ready",
    last_drop:"last_drop",
    data:"data",
    empty:"empty",
    wr_en:"wr_en",
    sewage_valve:"sewage_valve",
    axi_master:"axi_master",
    down_stream:nil,
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [axi_master].first.belong_to_module unless belong_to_module
    
    
    
    if down_stream.is_a? Axi4
        down_stream.idata_pool_axi4(
            dsize:dsize,
            source_addr:source_addr,
            size:size,
            valid:valid,
            ready:ready,
            last_drop:last_drop,
            data:data,
            empty:empty,
            wr_en:wr_en,
            sewage_valve:sewage_valve,
            axi_master:axi_master,
            down_stream:down_stream)
    elsif axi_master.is_a? Axi4
        axi_master.idata_pool_axi4(
            dsize:dsize,
            source_addr:source_addr,
            size:size,
            valid:valid,
            ready:ready,
            last_drop:last_drop,
            data:data,
            empty:empty,
            wr_en:wr_en,
            sewage_valve:sewage_valve,
            axi_master:axi_master,
            down_stream:down_stream)
    else
        belong_to_module.Axi4_NC.idata_pool_axi4(
            dsize:dsize,
            source_addr:source_addr,
            size:size,
            valid:valid,
            ready:ready,
            last_drop:last_drop,
            data:data,
            empty:empty,
            wr_en:wr_en,
            sewage_valve:sewage_valve,
            axi_master:axi_master,
            down_stream:down_stream)
    end
    return return_stream
end

.odata_pool_axi4(dsize: 8, rd_clk: "rd_clk", rd_rst_n: "rd_rst_n", data: "data", empty: "empty", rd_en: "rd_en", source_addr: "source_addr", size: "size", valid: "valid", ready: "ready", last_drop: "last_drop", axi_master: "axi_master") ⇒ Object 



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# File 'lib/tdl/axi4/odata_pool_axi4_auto.rb', line 104

def self.odata_pool_axi4(
    dsize:8,
    rd_clk:"rd_clk",
    rd_rst_n:"rd_rst_n",
    data:"data",
    empty:"empty",
    rd_en:"rd_en",
    source_addr:"source_addr",
    size:"size",
    valid:"valid",
    ready:"ready",
    last_drop:"last_drop",
    axi_master:"axi_master",
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [axi_master].first.belong_to_module unless belong_to_module
    
    
    belong_to_module.Axi4_NC._odata_pool_axi4(
        dsize:dsize,
        rd_clk:rd_clk,
        rd_rst_n:rd_rst_n,
        data:data,
        empty:empty,
        rd_en:rd_en,
        source_addr:source_addr,
        size:size,
        valid:valid,
        ready:ready,
        last_drop:last_drop,
        axi_master:axi_master)
    return return_stream
end

.odata_pool_axi4_a1(source_addr: "source_addr", size: "size", valid: "valid", ready: "ready", out_axis: "out_axis", axi_master: "axi_master") ⇒ Object 



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# File 'lib/tdl/axi4/odata_pool_axi4_A1_auto.rb', line 74

def self.odata_pool_axi4_a1(
    source_addr:"source_addr",
    size:"size",
    valid:"valid",
    ready:"ready",
    out_axis:"out_axis",
    axi_master:"axi_master",
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [axi_master].first.belong_to_module unless belong_to_module
    
    
    belong_to_module.Axi4_NC._odata_pool_axi4_a1(
        source_addr:source_addr,
        size:size,
        valid:valid,
        ready:ready,
        out_axis:out_axis,
        axi_master:axi_master)
    return return_stream
end

.parse_ports(port_array = nil) ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 372

def self.parse_ports(port_array=nil)
    rep = /(?<up_down>\(\*\s+(?<ud_name>axi4_up|axi4_down)\s*=\s*"true"\s+\*\))?\s*(axi_inf\.)(?<modport>master|slaver|master_wr|slaver_wr|master_rd|slaver_rd|master_wr_aux|master_wr_aux_no_resp|master_rd_aux|mirror_wr|mirror_rd)\s+(?<name>\w+)\s*(?<vector>\[.*?\])?/m
    up_stream_rep = /axi4_up/

    super(port_array,rep,"axi_inf",up_stream_rep) do |h|
        h[:type]   = Axi4
        yield h
    end
end

.same_name_socket(way, mix, inf_array, base_new_inf = nil, belong_to_module = nil) ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 386

def self.same_name_socket(way,mix,inf_array,base_new_inf=nil,belong_to_module=nil)
    ##----
    unless inf_array.is_a? Array
        return inf_array if inf_array.respond_to?(:dimension) && inf_array.dimension.any?
        inf_array = [inf_array]
    end

    return nil if inf_array.empty?

    return inf_array[0] if (inf_array.length == 1 && mix==true)
    ## =====
    unless base_new_inf
        if mix
            new_inf = inf_array[0].copy(idsize:(inf_array[0].idsize + inf_array.length.clog2 ))
        else
            new_inf = inf_array[0].copy()
        end
    else
        new_inf = base_new_inf
    end

    super(way,mix,inf_array,new_inf,belong_to_module)
end

.sync_mode(up_stream: nil, down_stream: nil) ⇒ Object

mode trans =======================================================



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# File 'lib/tdl/elements/axi4.rb', line 249

def self.sync_mode(up_stream:nil,down_stream:nil)
    if up_stream.mode == down_stream.mode
        return [up_stream,down_stream]
    elsif up_stream.mode != BOTH
        return [up_stream,down_stream.sync_mode(up_stream:up_stream)]
    elsif down_stream.mode != BOTH
        return [up_stream.sync_mode(down_stream:down_stream),down_stream]
    end
end

.video_from_axi4(axi4_master: nil, video_slaver: nil, video_master: nil, mode: "LINE", base_addr: nil) ⇒ Object 



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# File 'lib/tdl/VideoInf/video_from_axi4.rb', line 90

def self.video_from_axi4(axi4_master:nil,video_slaver:nil,video_master:nil,mode:"LINE",base_addr:nil)
    VideoInf.video_from_axi4(axi4_master:axi4_master,video_slaver:video_slaver,video_master:video_master,mode:mode,base_addr:base_addr)
end

.video_to_axi4(axi4_master: nil, video_slaver: nil, mode: "LINE", base_addr: nil) ⇒ Object 



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# File 'lib/tdl/VideoInf/video_to_axi4.rb', line 57

def self.video_to_axi4(axi4_master:nil,video_slaver:nil,mode:"LINE",base_addr:nil)
    VideoInf.video_to_axi4(axi4_master:axi4_master,video_slaver:video_slaver,mode:mode,base_addr:base_addr)
end

.video_to_vdma(mode: "LINE", base_addr: "base_addr", video_inf: "video_inf", axi_master: "axi_master", down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi_stream/bak/video_to_VDMA.rb', line 31

def self.video_to_vdma(mode:"LINE",base_addr:"base_addr",video_inf:"video_inf",axi_master:"axi_master",down_stream:nil)

    if down_stream.is_a? Axi4
        down_stream.video_to_vdma(mode:mode,base_addr:base_addr,video_inf:video_inf,axi_master:axi_master,down_stream:down_stream)
    elsif axi_master.is_a? Axi4
        axi_master.video_to_vdma(mode:mode,base_addr:base_addr,video_inf:video_inf,axi_master:axi_master,down_stream:down_stream)
    else
        NC.video_to_vdma(mode:mode,base_addr:base_addr,video_inf:video_inf,axi_master:axi_master,down_stream:down_stream)
    end

end

Instance Method Details

#<<(*up_streams) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_interconnect_verb.rb', line 62

def <<(*up_streams)
    require_shdl 'axi4_direct_algin_addr_step'
    up_streams.each do |up_stream|
        ## e is a Vector 
        if up_stream.is_a? Axi4
            if up_stream.dimension && up_stream.dimension[0].is_a?(Integer) && up_stream.dimension[0] > 1
                self.belong_to_module.instance_exec(self,up_stream) do |curr_axi4_inst,up_stream|
                    up_stream.copy(
                        name: "#{up_stream.inst_name}_algin_addr",
                        addr_step: curr_axi4_inst.addr_step*up_stream.dsize/curr_axi4_inst.dsize,
                        dimension:up_stream.dimension)

                    generate(up_stream.dimension[0]) do |kk|   
                        Instance(:axi4_direct_algin_addr_step,"algin_addr_#{up_stream.inst_name}_#{curr_axi4_inst.name}") do |h| #(
                            h.param.SLAVER_ADDR_STEP    up_stream.addr_step
                            h.param.TERMENAL_ADDR_STEP  curr_axi4_inst.addr_step
                            h.param.TERMENAL_DSIZE      curr_axi4_inst.dsize
                            h.param.MODE            "#{up_stream.mode}_to_#{up_stream.mode}"    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
                            h.param.SLAVER_MODE     up_stream.mode    
                            h.param.MASTER_MODE     up_stream.mode    
                            h.port.axi_inf.slaver.slaver_inf     up_stream[kk]
                            h.port.axi_inf.master.master_inf     curr_axi4_inst.belong_to_module.signal("#{up_stream.inst_name}_algin_addr")[kk]
                        end
                    end
                    curr_axi4_inst.old_append( signal("#{up_stream.inst_name}_algin_addr") )
                end
            else  
                curr_axi4_inst = self
                up_stream.copy(
                    name: "#{up_stream.inst_name}_algin_addr",
                    addr_step: curr_axi4_inst.addr_step*up_stream.dsize/curr_axi4_inst.dsize)

                self.belong_to_module.Instance(:axi4_direct_algin_addr_step,"algin_addr_#{up_stream.inst_name}_#{name}_#{belong_to_module._auto_name_incr_index_}") do |h| #(
                    h.param.SLAVER_ADDR_STEP    up_stream.addr_step
                    h.param.TERMENAL_ADDR_STEP  curr_axi4_inst.addr_step
                    h.param.TERMENAL_DSIZE      curr_axi4_inst.dsize
                    h.param.MODE            "#{up_stream.mode}_to_#{up_stream.mode}"    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
                    h.param.SLAVER_MODE     up_stream.mode    
                    h.param.MASTER_MODE     up_stream.mode    
                    h.port.axi_inf.slaver.slaver_inf     up_stream
                    h.port.axi_inf.master.master_inf      self.belong_to_module.signal("#{up_stream.inst_name}_algin_addr")
                
                end
                curr_axi4_inst.old_append(  self.belong_to_module.signal("#{up_stream.inst_name}_algin_addr") )
            end
        else 
            self.old_append(up_stream)
        end
    end

end

#>>(down_stream) ⇒ Object

def idsize=(n)

@idsize = n
# cal_idsize_asize

end



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# File 'lib/tdl/axi4/axi4_interconnect_verb.rb', line 58

def >>(down_stream)
    down_stream.<< self
end

#[](a) ⇒ Object

Raises:



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# File 'lib/tdl/elements/axi4.rb', line 606

def [](a)
    if a.is_a? ClassHDL::OpertorChain
        a.slaver = true
    end

    raise TdlError.new("#{signal} isn't vector") if dimension.empty?
    signal(a)
end

#__inf_signal__(name) ⇒ Object

Raises:



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# File 'lib/tdl/elements/axi4.rb', line 414

def __inf_signal__(name)
    raise TdlError.new("\nARRAY Don't have '#{name}'\n") unless @dimension.empty?
    # puts "--------------"
    # puts $new_m.instance_variable_get("@port_axisinfs")
    # puts "============="
    NqString.new(signal.concat ".#{name}")
    # signal.concat ".#{name}"
end

#_axi4_combin_wr_rd_batch(wr_slaver: "wr_slaver", rd_slaver: "rd_slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb', line 9

def _axi4_combin_wr_rd_batch(
    wr_slaver:"wr_slaver",
    rd_slaver:"rd_slaver",
    master:"master"
)

    Tdl.add_to_all_file_paths('axi4_combin_wr_rd_batch','../../axi/AXI4/axi4_combin_wr_rd_batch.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi4_combin_wr_rd_batch','../../axi/AXI4/axi4_combin_wr_rd_batch.sv'])
    return_stream = self
    
    wr_slaver = Axi4.same_name_socket(:mirror,mix=true,wr_slaver,nil,belong_to_module) unless wr_slaver.is_a? String
    rd_slaver = Axi4.same_name_socket(:mirror,mix=true,rd_slaver,nil,belong_to_module) unless rd_slaver.is_a? String
    master = Axi4.same_name_socket(:to_down,mix=true,master,nil,belong_to_module) unless master.is_a? String
    
    
    


    belong_to_module.Axi4_draw << _axi4_combin_wr_rd_batch_draw(
        wr_slaver:wr_slaver,
        rd_slaver:rd_slaver,
        master:master)
    return return_stream
end

#_axi4_combin_wr_rd_batch_draw(wr_slaver: "wr_slaver", rd_slaver: "rd_slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb', line 36

def _axi4_combin_wr_rd_batch_draw(
    wr_slaver:"wr_slaver",
    rd_slaver:"rd_slaver",
    master:"master"
)

    large_name_len(
        wr_slaver,
        rd_slaver,
        master
    )
    instance_name = "axi4_combin_wr_rd_batch_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/axi4_combin_wr_rd_batch.sv
axi4_combin_wr_rd_batch #{instance_name}(
/*  axi_inf.slaver_wr*/ .wr_slaver (#{align_signal(wr_slaver,q_mark=false)}),
/*  axi_inf.slaver_rd*/ .rd_slaver (#{align_signal(rd_slaver,q_mark=false)}),
/*  axi_inf.master   */ .master    (#{align_signal(master,q_mark=false)})
);
"
end

#_axi4_direct(mode: "BOTH_to_BOTH", slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_direct_auto.rb', line 9

def _axi4_direct(
    mode:"BOTH_to_BOTH",
    slaver:"slaver",
    master:"master"
)

    Tdl.add_to_all_file_paths('axi4_direct','../../axi/AXI4/axi4_direct.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi4_direct','../../axi/AXI4/axi4_direct.sv'])
    return_stream = self
    
    slaver = Axi4.same_name_socket(:from_up,mix=true,slaver,nil,belong_to_module) unless slaver.is_a? String
    master = Axi4.same_name_socket(:to_down,mix=true,master,nil,belong_to_module) unless master.is_a? String
    
    
    


    belong_to_module.Axi4_draw << _axi4_direct_draw(
        mode:mode,
        slaver:slaver,
        master:master)
    return return_stream
end

#_axi4_direct_draw(mode: "BOTH_to_BOTH", slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_direct_auto.rb', line 35

def _axi4_direct_draw(
    mode:"BOTH_to_BOTH",
    slaver:"slaver",
    master:"master"
)

    large_name_len(
        mode,
        slaver,
        master
    )
    instance_name = "axi4_direct_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/axi4_direct.sv
axi4_direct#(
.MODE    (#{align_signal(mode)})
) #{instance_name}(
/*  axi_inf.slaver*/ .slaver (#{align_signal(slaver,q_mark=false)}),
/*  axi_inf.master*/ .master (#{align_signal(master,q_mark=false)})
);
"
end

#_axi4_direct_verb(slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_direct_verb_auto.rb', line 9

def _axi4_direct_verb(
    slaver:"slaver",
    master:"master"
)

    Tdl.add_to_all_file_paths('axi4_direct_verb','../../axi/AXI4/axi4_direct_verb.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi4_direct_verb','../../axi/AXI4/axi4_direct_verb.sv'])
    return_stream = self
    
    slaver = Axi4.same_name_socket(:from_up,mix=true,slaver,nil,belong_to_module) unless slaver.is_a? String
    master = Axi4.same_name_socket(:to_down,mix=true,master,nil,belong_to_module) unless master.is_a? String
    
    
    


    belong_to_module.Axi4_draw << _axi4_direct_verb_draw(
        slaver:slaver,
        master:master)
    return return_stream
end

#_axi4_direct_verb_draw(slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_direct_verb_auto.rb', line 33

def _axi4_direct_verb_draw(
    slaver:"slaver",
    master:"master"
)

    large_name_len(
        slaver,
        master
    )
    instance_name = "axi4_direct_verb_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/axi4_direct_verb.sv
axi4_direct_verb #{instance_name}(
/*  axi_inf.slaver*/ .slaver (#{align_signal(slaver,q_mark=false)}),
/*  axi_inf.master*/ .master (#{align_signal(master,q_mark=false)})
);
"
end

#_axi4_long_to_axi4_wide(slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb', line 9

def _axi4_long_to_axi4_wide(
    slaver:"slaver",
    master:"master"
)

    Tdl.add_to_all_file_paths('axi4_long_to_axi4_wide','../../axi/AXI4/axi4_long_to_axi4_wide.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi4_long_to_axi4_wide','../../axi/AXI4/axi4_long_to_axi4_wide.sv'])
    return_stream = self
    
    slaver = Axi4.same_name_socket(:from_up,mix=true,slaver,nil,belong_to_module) unless slaver.is_a? String
    master = Axi4.same_name_socket(:to_down,mix=true,master,nil,belong_to_module) unless master.is_a? String
    
    
    


    belong_to_module.Axi4_draw << _axi4_long_to_axi4_wide_draw(
        slaver:slaver,
        master:master)
    return return_stream
end

#_axi4_long_to_axi4_wide_a1(partition: "ON", slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb', line 9

def _axi4_long_to_axi4_wide_a1(
    partition:"ON",
    slaver:"slaver",
    master:"master"
)

    Tdl.add_to_all_file_paths('axi4_long_to_axi4_wide_a1','../../axi/AXI4/axi4_long_to_axi4_wide_A1.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi4_long_to_axi4_wide_a1','../../axi/AXI4/axi4_long_to_axi4_wide_A1.sv'])
    return_stream = self
    
    slaver = Axi4.same_name_socket(:from_up,mix=true,slaver,nil,belong_to_module) unless slaver.is_a? String
    master = Axi4.same_name_socket(:to_down,mix=true,master,nil,belong_to_module) unless master.is_a? String
    
    
    


    belong_to_module.Axi4_draw << _axi4_long_to_axi4_wide_a1_draw(
        partition:partition,
        slaver:slaver,
        master:master)
    return return_stream
end

#_axi4_long_to_axi4_wide_a1_draw(partition: "ON", slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb', line 35

def _axi4_long_to_axi4_wide_a1_draw(
    partition:"ON",
    slaver:"slaver",
    master:"master"
)

    large_name_len(
        partition,
        slaver,
        master
    )
    instance_name = "axi4_long_to_axi4_wide_A1_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/axi4_long_to_axi4_wide_A1.sv
axi4_long_to_axi4_wide_A1#(
.PARTITION    (#{align_signal(partition)})
) #{instance_name}(
/*  axi_inf.slaver*/ .slaver (#{align_signal(slaver,q_mark=false)}),
/*  axi_inf.master*/ .master (#{align_signal(master,q_mark=false)})
);
"
end

#_axi4_long_to_axi4_wide_draw(slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb', line 33

def _axi4_long_to_axi4_wide_draw(
    slaver:"slaver",
    master:"master"
)

    large_name_len(
        slaver,
        master
    )
    instance_name = "axi4_long_to_axi4_wide_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/axi4_long_to_axi4_wide.sv
axi4_long_to_axi4_wide #{instance_name}(
/*  axi_inf.slaver*/ .slaver (#{align_signal(slaver,q_mark=false)}),
/*  axi_inf.master*/ .master (#{align_signal(master,q_mark=false)})
);
"
end

#_axi4_long_to_axi4_wide_verb(pipe: "OFF", partition: "ON", slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb', line 9

def _axi4_long_to_axi4_wide_verb(
    pipe:"OFF",
    partition:"ON",
    slaver:"slaver",
    master:"master"
)

    Tdl.add_to_all_file_paths('axi4_long_to_axi4_wide_verb','../../axi/AXI4/axi4_long_to_axi4_wide_verb.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi4_long_to_axi4_wide_verb','../../axi/AXI4/axi4_long_to_axi4_wide_verb.sv'])
    return_stream = self
    
    slaver = Axi4.same_name_socket(:from_up,mix=true,slaver,nil,belong_to_module) unless slaver.is_a? String
    master = Axi4.same_name_socket(:to_down,mix=true,master,nil,belong_to_module) unless master.is_a? String
    
    
    


    belong_to_module.Axi4_draw << _axi4_long_to_axi4_wide_verb_draw(
        pipe:pipe,
        partition:partition,
        slaver:slaver,
        master:master)
    return return_stream
end

#_axi4_long_to_axi4_wide_verb_draw(pipe: "OFF", partition: "ON", slaver: "slaver", master: "master") ⇒ Object 



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# File 'lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb', line 37

def _axi4_long_to_axi4_wide_verb_draw(
    pipe:"OFF",
    partition:"ON",
    slaver:"slaver",
    master:"master"
)

    large_name_len(
        pipe,
        partition,
        slaver,
        master
    )
    instance_name = "axi4_long_to_axi4_wide_verb_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/axi4_long_to_axi4_wide_verb.sv
axi4_long_to_axi4_wide_verb#(
.PIPE         (#{align_signal(pipe)}),
.PARTITION    (#{align_signal(partition)})
) #{instance_name}(
/*  axi_inf.slaver*/ .slaver (#{align_signal(slaver,q_mark=false)}),
/*  axi_inf.master*/ .master (#{align_signal(master,q_mark=false)})
);
"
end

#_axi4_to_native_for_ddr_ip_verb(addr_width: 27, data_width: 256, app_addr: "app_addr", app_cmd: "app_cmd", app_en: "app_en", app_wdf_data: "app_wdf_data", app_wdf_end: "app_wdf_end", app_wdf_mask: "app_wdf_mask", app_wdf_wren: "app_wdf_wren", app_rd_data: "app_rd_data", app_rd_data_end: "app_rd_data_end", app_rd_data_valid: "app_rd_data_valid", app_rdy: "app_rdy", app_wdf_rdy: "app_wdf_rdy", init_calib_complete: "init_calib_complete", axi_inf: "axi_inf") ⇒ Object 



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# File 'lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb', line 9

def _axi4_to_native_for_ddr_ip_verb(addr_width:27,data_width:256,app_addr:"app_addr",app_cmd:"app_cmd",app_en:"app_en",app_wdf_data:"app_wdf_data",app_wdf_end:"app_wdf_end",app_wdf_mask:"app_wdf_mask",app_wdf_wren:"app_wdf_wren",app_rd_data:"app_rd_data",app_rd_data_end:"app_rd_data_end",app_rd_data_valid:"app_rd_data_valid",app_rdy:"app_rdy",app_wdf_rdy:"app_wdf_rdy",init_calib_complete:"init_calib_complete",axi_inf:"axi_inf")
    return_stream = self
    
    
    

    $_draw = lambda { _axi4_to_native_for_ddr_ip_verb_draw(addr_width:addr_width,data_width:data_width,app_addr:app_addr,app_cmd:app_cmd,app_en:app_en,app_wdf_data:app_wdf_data,app_wdf_end:app_wdf_end,app_wdf_mask:app_wdf_mask,app_wdf_wren:app_wdf_wren,app_rd_data:app_rd_data,app_rd_data_end:app_rd_data_end,app_rd_data_valid:app_rd_data_valid,app_rdy:app_rdy,app_wdf_rdy:app_wdf_rdy,init_calib_complete:init_calib_complete,axi_inf:axi_inf) }
    @correlation_proc += $_draw.call
    return return_stream
end

#_axi4_to_native_for_ddr_ip_verb_draw(addr_width: 27, data_width: 256, app_addr: "app_addr", app_cmd: "app_cmd", app_en: "app_en", app_wdf_data: "app_wdf_data", app_wdf_end: "app_wdf_end", app_wdf_mask: "app_wdf_mask", app_wdf_wren: "app_wdf_wren", app_rd_data: "app_rd_data", app_rd_data_end: "app_rd_data_end", app_rd_data_valid: "app_rd_data_valid", app_rdy: "app_rdy", app_wdf_rdy: "app_wdf_rdy", init_calib_complete: "init_calib_complete", axi_inf: "axi_inf") ⇒ Object 



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# File 'lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb', line 20

def _axi4_to_native_for_ddr_ip_verb_draw(addr_width:27,data_width:256,app_addr:"app_addr",app_cmd:"app_cmd",app_en:"app_en",app_wdf_data:"app_wdf_data",app_wdf_end:"app_wdf_end",app_wdf_mask:"app_wdf_mask",app_wdf_wren:"app_wdf_wren",app_rd_data:"app_rd_data",app_rd_data_end:"app_rd_data_end",app_rd_data_valid:"app_rd_data_valid",app_rdy:"app_rdy",app_wdf_rdy:"app_wdf_rdy",init_calib_complete:"init_calib_complete",axi_inf:"axi_inf")
    large_name_len(addr_width,data_width,app_addr,app_cmd,app_en,app_wdf_data,app_wdf_end,app_wdf_mask,app_wdf_wren,app_rd_data,app_rd_data_end,app_rd_data_valid,app_rdy,app_wdf_rdy,init_calib_complete,axi_inf)
"
axi4_to_native_for_ddr_ip_verb#(
.ADDR_WIDTH    (#{align_signal(addr_width)}),
.DATA_WIDTH    (#{align_signal(data_width)})
) axi4_to_native_for_ddr_ip_verb_#{signal}_inst(
/*  output [ADDR_WIDTH-1:0]  */ .app_addr            (#{align_signal(app_addr,q_mark=false)}),
/*  output [2:0]             */ .app_cmd             (#{align_signal(app_cmd,q_mark=false)}),
/*  output                   */ .app_en              (#{align_signal(app_en,q_mark=false)}),
/*  output [DATA_WIDTH-1:0]  */ .app_wdf_data        (#{align_signal(app_wdf_data,q_mark=false)}),
/*  output                   */ .app_wdf_end         (#{align_signal(app_wdf_end,q_mark=false)}),
/*  output [DATA_WIDTH/8-1:0]*/ .app_wdf_mask        (#{align_signal(app_wdf_mask,q_mark=false)}),
/*  output                   */ .app_wdf_wren        (#{align_signal(app_wdf_wren,q_mark=false)}),
/*  input  [DATA_WIDTH-1:0]  */ .app_rd_data         (#{align_signal(app_rd_data,q_mark=false)}),
/*  input                    */ .app_rd_data_end     (#{align_signal(app_rd_data_end,q_mark=false)}),
/*  input                    */ .app_rd_data_valid   (#{align_signal(app_rd_data_valid,q_mark=false)}),
/*  input                    */ .app_rdy             (#{align_signal(app_rdy,q_mark=false)}),
/*  input                    */ .app_wdf_rdy         (#{align_signal(app_wdf_rdy,q_mark=false)}),
/*  input                    */ .init_calib_complete (#{align_signal(init_calib_complete,q_mark=false)}),
/*  axi_inf.slaver           */ .axi_inf             (#{align_signal(axi_inf,q_mark=false)})
);
"
end

#_axi_data(name, h = nil, l = nil) ⇒ Object

def vld_rdy

axis_tvalid.concat(" && ").concat(axis_tready)

end

def vld_rdy_last

axis_tvalid.concat(" && ").concat(axis_tready).concat(" && ").concat(axis_tlast)

end

Raises:



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# File 'lib/tdl/elements/axi4.rb', line 475

def _axi_data(name,h=nil,l=nil)
    raise TdlError.new("\nARRAY Don't have '#{name}'") unless @dimension.empty?

    if h.is_a? Range
        l = h.to_a.min
        h = h.to_a.max
    end

    if h
        if l
            sqr = "[#{h.to_s}:#{l.to_s}]"
        else
            sqr = "[#{h.to_s}]"
        end
    else
        sqr = ""
    end
    NqString.new(signal.concat(".#{name}").concat(sqr))
end

#_odata_pool_axi4(dsize: 8, rd_clk: "rd_clk", rd_rst_n: "rd_rst_n", data: "data", empty: "empty", rd_en: "rd_en", source_addr: "source_addr", size: "size", valid: "valid", ready: "ready", last_drop: "last_drop", axi_master: "axi_master") ⇒ Object 



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# File 'lib/tdl/axi4/odata_pool_axi4_auto.rb', line 9

def _odata_pool_axi4(
    dsize:8,
    rd_clk:"rd_clk",
    rd_rst_n:"rd_rst_n",
    data:"data",
    empty:"empty",
    rd_en:"rd_en",
    source_addr:"source_addr",
    size:"size",
    valid:"valid",
    ready:"ready",
    last_drop:"last_drop",
    axi_master:"axi_master"
)

    Tdl.add_to_all_file_paths('odata_pool_axi4','../../axi/AXI4/odata_pool_axi4.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['odata_pool_axi4','../../axi/AXI4/odata_pool_axi4.sv'])
    return_stream = self
    
    axi_master = Axi4.same_name_socket(:mirror,mix=true,axi_master,nil,belong_to_module) unless axi_master.is_a? String
    
    
    


    belong_to_module.Axi4_draw << _odata_pool_axi4_draw(
        dsize:dsize,
        rd_clk:rd_clk,
        rd_rst_n:rd_rst_n,
        data:data,
        empty:empty,
        rd_en:rd_en,
        source_addr:source_addr,
        size:size,
        valid:valid,
        ready:ready,
        last_drop:last_drop,
        axi_master:axi_master)
    return return_stream
end

#_odata_pool_axi4_a1(source_addr: "source_addr", size: "size", valid: "valid", ready: "ready", out_axis: "out_axis", axi_master: "axi_master") ⇒ Object 



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# File 'lib/tdl/axi4/odata_pool_axi4_A1_auto.rb', line 9

def _odata_pool_axi4_a1(
    source_addr:"source_addr",
    size:"size",
    valid:"valid",
    ready:"ready",
    out_axis:"out_axis",
    axi_master:"axi_master"
)

    Tdl.add_to_all_file_paths('odata_pool_axi4_a1','../../axi/AXI4/odata_pool_axi4_A1.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['odata_pool_axi4_a1','../../axi/AXI4/odata_pool_axi4_A1.sv'])
    return_stream = self
    
    out_axis = AxiStream.same_name_socket(:to_down,mix=true,out_axis,nil,belong_to_module) unless out_axis.is_a? String
    axi_master = Axi4.same_name_socket(:mirror,mix=true,axi_master,nil,belong_to_module) unless axi_master.is_a? String
    
    
    


    belong_to_module.Axi4_draw << _odata_pool_axi4_a1_draw(
        source_addr:source_addr,
        size:size,
        valid:valid,
        ready:ready,
        out_axis:out_axis,
        axi_master:axi_master)
    return return_stream
end

#_odata_pool_axi4_a1_draw(source_addr: "source_addr", size: "size", valid: "valid", ready: "ready", out_axis: "out_axis", axi_master: "axi_master") ⇒ Object 



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# File 'lib/tdl/axi4/odata_pool_axi4_A1_auto.rb', line 41

def _odata_pool_axi4_a1_draw(
    source_addr:"source_addr",
    size:"size",
    valid:"valid",
    ready:"ready",
    out_axis:"out_axis",
    axi_master:"axi_master"
)

    large_name_len(
        source_addr,
        size,
        valid,
        ready,
        out_axis,
        axi_master
    )
    instance_name = "odata_pool_axi4_A1_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/odata_pool_axi4_A1.sv
odata_pool_axi4_A1 #{instance_name}(
/*  input  [31:0]        */ .source_addr (#{align_signal(source_addr,q_mark=false)}),
/*  input  [31:0]        */ .size        (#{align_signal(size,q_mark=false)}),
/*  input                */ .valid       (#{align_signal(valid,q_mark=false)}),
/*  output               */ .ready       (#{align_signal(ready,q_mark=false)}),
/*  axi_stream_inf.master*/ .out_axis    (#{align_signal(out_axis,q_mark=false)}),
/*  axi_inf.master_rd    */ .axi_master  (#{align_signal(axi_master,q_mark=false)})
);
"
end

#_odata_pool_axi4_draw(dsize: 8, rd_clk: "rd_clk", rd_rst_n: "rd_rst_n", data: "data", empty: "empty", rd_en: "rd_en", source_addr: "source_addr", size: "size", valid: "valid", ready: "ready", last_drop: "last_drop", axi_master: "axi_master") ⇒ Object 



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# File 'lib/tdl/axi4/odata_pool_axi4_auto.rb', line 52

def _odata_pool_axi4_draw(
    dsize:8,
    rd_clk:"rd_clk",
    rd_rst_n:"rd_rst_n",
    data:"data",
    empty:"empty",
    rd_en:"rd_en",
    source_addr:"source_addr",
    size:"size",
    valid:"valid",
    ready:"ready",
    last_drop:"last_drop",
    axi_master:"axi_master"
)

    large_name_len(
        dsize,
        rd_clk,
        rd_rst_n,
        data,
        empty,
        rd_en,
        source_addr,
        size,
        valid,
        ready,
        last_drop,
        axi_master
    )
    instance_name = "odata_pool_axi4_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/odata_pool_axi4.sv
odata_pool_axi4#(
.DSIZE    (#{align_signal(dsize)})
) #{instance_name}(
/*  input             */ .rd_clk      (#{align_signal(rd_clk,q_mark=false)}),
/*  input             */ .rd_rst_n    (#{align_signal(rd_rst_n,q_mark=false)}),
/*  output [DSIZE-1:0]*/ .data        (#{align_signal(data,q_mark=false)}),
/*  output            */ .empty       (#{align_signal(empty,q_mark=false)}),
/*  input             */ .rd_en       (#{align_signal(rd_en,q_mark=false)}),
/*  input  [31:0]     */ .source_addr (#{align_signal(source_addr,q_mark=false)}),
/*  input  [31:0]     */ .size        (#{align_signal(size,q_mark=false)}),
/*  input             */ .valid       (#{align_signal(valid,q_mark=false)}),
/*  output            */ .ready       (#{align_signal(ready,q_mark=false)}),
/*  output            */ .last_drop   (#{align_signal(last_drop,q_mark=false)}),
/*  axi_inf.master_rd */ .axi_master  (#{align_signal(axi_master,q_mark=false)})
);
"
end

#axi4_data_convert(up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/bak/axi4_data_convert.rb', line 7

def axi4_data_convert(up_stream:nil,down_stream:nil)
    if down_stream && !up_stream
        down_stream.axi4_data_convert(up_stream:self,down_stream:down_stream)
        return down_stream
    end

    down_stream = self

    up_stream,down_stream = Axi4::sync_mode(up_stream:up_stream,down_stream:down_stream)

    if up_stream.dsize == down_stream.dsize
        $_draw = lambda { axi4_direct_draw(up_stream:up_stream,down_stream:down_stream) }
    else
        $_draw = lambda { axi4_data_convert_draw(up_stream:up_stream,down_stream:down_stream) }
    end
    @correlation_proc +=$_draw.call
    return self
end

#axi4_data_convert_draw(up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/bak/axi4_data_convert.rb', line 26

def axi4_data_convert_draw(up_stream:nil,down_stream:nil)
    large_name_len(up_stream,down_stream)
"\naxi4_data_convert axi4_data_convert_#{signal}_inst(
/* axi_inf.slaver */ .axi_in    (#{align_signal(up_stream)}),
/* axi_inf.master */ .axi_out   (#{align_signal(down_stream)})
);\n"
end

#axi4_direct(up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_direct.rb', line 6

def axi4_direct(up_stream:nil,down_stream:nil)
    if down_stream && !up_stream
        down_stream.axi4_direct(up_stream:self,down_stream:down_stream)
        return down_stream
    end

    down_stream = self

    # $_draw = lambda { axi4_direct_draw(up_stream:up_stream,down_stream:down_stream) }
    # @correlation_proc +=$_draw.call

    belong_to_module.Axi4_draw << axi4_direct_draw(up_stream:up_stream,down_stream:down_stream)
    return self
end

#axi4_direct_a1(mode: "BOTH_to_BOTH", slaver: "slaver", master: "master", up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_direct_A1_auto.rb', line 9

def axi4_direct_a1(
    mode:"BOTH_to_BOTH",
    slaver:"slaver",
    master:"master",
    up_stream:nil,
    down_stream:nil
)

    Tdl.add_to_all_file_paths('axi4_direct_a1','../../axi/AXI4/axi4_direct_A1.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi4_direct_a1','../../axi/AXI4/axi4_direct_A1.sv'])
    return_stream = self
    
    slaver = Axi4.same_name_socket(:from_up,mix=true,slaver,nil,belong_to_module) unless slaver.is_a? String
    master = Axi4.same_name_socket(:to_down,mix=true,master,nil,belong_to_module) unless master.is_a? String
    
    if up_stream.nil? && slaver.eql?("slaver") && (!(master.eql?("master")) || !down_stream.nil?)
        # up_stream = self.copy(name:"slaver")
        # return_stream = up_stream
        master = down_stream if down_stream
        return down_stream.axi4_direct_a1(slaver:self)
    end

    slaver = up_stream if up_stream
    unless self.eql? belong_to_module.Axi4_NC
        master = self
    else
        if down_stream
            master = down_stream
        end
    end


    belong_to_module.Axi4_draw << axi4_direct_a1_draw(
        mode:mode,
        slaver:slaver,
        master:master,
        up_stream:up_stream,
        down_stream:down_stream)
    return return_stream
end

#axi4_direct_draw(up_stream: nil, down_stream: self) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_direct.rb', line 21

def axi4_direct_draw(up_stream:nil,down_stream:self)
    dmode = up_stream.mode+"_to_"+down_stream.mode
    large_name_len(dmode,up_stream,down_stream)
"\naxi4_direct #(
.MODE       (#{align_signal(dmode)})    //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
)axi4_direct_#{signal}_inst(
/* axi_inf.slaver */  .slaver   (#{align_signal(up_stream)}),
/* axi_inf.master */  .master   (#{align_signal(down_stream)})
);\n"
end

#axi4_packet_fifo(pipe: "OFF", depth: 4, mode: "BOTH", axi_in: "axi_in", axi_out: "axi_out", up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_packet_fifo_auto.rb', line 9

def axi4_packet_fifo(
    pipe:"OFF",
    depth:4,
    mode:"BOTH",
    axi_in:"axi_in",
    axi_out:"axi_out",
    up_stream:nil,
    down_stream:nil
)

    Tdl.add_to_all_file_paths('axi4_packet_fifo','../../axi/AXI4/packet_fifo/axi4_packet_fifo.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi4_packet_fifo','../../axi/AXI4/packet_fifo/axi4_packet_fifo.sv'])
    return_stream = self
    
    axi_in = Axi4.same_name_socket(:from_up,mix=true,axi_in,nil,belong_to_module) unless axi_in.is_a? String
    axi_out = Axi4.same_name_socket(:to_down,mix=true,axi_out,nil,belong_to_module) unless axi_out.is_a? String
    
    if up_stream.nil? && axi_in.eql?("axi_in") && (!(axi_out.eql?("axi_out")) || !down_stream.nil?)
        # up_stream = self.copy(name:"axi_in")
        # return_stream = up_stream
        axi_out = down_stream if down_stream
        return down_stream.axi4_packet_fifo(axi_in:self)
    end

    axi_in = up_stream if up_stream
    unless self.eql? belong_to_module.Axi4_NC
        axi_out = self
    else
        if down_stream
            axi_out = down_stream
        end
    end


    belong_to_module.Axi4_draw << axi4_packet_fifo_draw(
        pipe:pipe,
        depth:depth,
        mode:mode,
        axi_in:axi_in,
        axi_out:axi_out,
        up_stream:up_stream,
        down_stream:down_stream)
    return return_stream
end

#axi4_packet_fifo_draw(pipe: "OFF", depth: 4, mode: "BOTH", axi_in: "axi_in", axi_out: "axi_out", up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_packet_fifo_auto.rb', line 56

def axi4_packet_fifo_draw(
    pipe:"OFF",
    depth:4,
    mode:"BOTH",
    axi_in:"axi_in",
    axi_out:"axi_out",
    up_stream:nil,
    down_stream:nil
)

    large_name_len(
        pipe,
        depth,
        mode,
        axi_in,
        axi_out
    )
    instance_name = "axi4_packet_fifo_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/packet_fifo/axi4_packet_fifo.sv
axi4_packet_fifo#(
.PIPE     (#{align_signal(pipe)}),
.DEPTH    (#{align_signal(depth)}),
.MODE     (#{align_signal(mode)})
) #{instance_name}(
/*  axi_inf.slaver*/ .axi_in  (#{align_signal(axi_in,q_mark=false)}),
/*  axi_inf.master*/ .axi_out (#{align_signal(axi_out,q_mark=false)})
);
"
end

#axi4_partition_od(up_stream: nil, down_stream: nil, addr_step: "1.0") ⇒ Object 



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# File 'lib/tdl/axi4/bak/axi4_partition_od.rb', line 7

def axi4_partition_od(up_stream:nil,down_stream:nil,addr_step:"1.0")

    if down_stream && !up_stream
        down_stream.axi4_partition_od(up_stream:self,down_stream:down_stream,addr_step:addr_step)
        return down_stream
    end

    down_stream = self

    up_stream,down_stream = Axi4::sync_mode(up_stream:up_stream,down_stream:down_stream)

    # if(up_stream.dsize != down_stream.dsize)
    #     cv_down_stream = Axi4::axi4_data_convert(up_stream:up_stream,dsize:down_stream.dsize)
    # else
    #     cv_down_stream = up_stream
    # end
    cv_down_stream = up_stream
    $_draw = lambda { axi4_partition_od_draw(up_stream:cv_down_stream,down_stream:down_stream,addr_step:addr_step) }
    @correlation_proc +=$_draw.call
    return self
end

#axi4_partition_od_draw(up_stream: nil, down_stream: self, addr_step: "1.0") ⇒ Object 



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# File 'lib/tdl/axi4/bak/axi4_partition_od.rb', line 29

def axi4_partition_od_draw(up_stream:nil,down_stream:self,addr_step:"1.0")
    large_name_len(up_stream,down_stream)
"\naxi4_partition_OD #(
.PSIZE          (#{down_stream.max_len}),
.ADDR_STEP      (#{addr_step})
)axi4_partition_OD_#{signal}_inst(
/*  axi_inf.slaver */   .slaver     (#{align_signal(up_stream)}),
/*  axi_inf.master */   .master     (#{align_signal(down_stream)})
);\n"
end

#axi4_pipe(slaver: "slaver", master: "master", up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_pipe_auto.rb', line 9

def axi4_pipe(
    slaver:"slaver",
    master:"master",
    up_stream:nil,
    down_stream:nil
)

    Tdl.add_to_all_file_paths('axi4_pipe','../../axi/AXI4/axi4_pipe/axi4_pipe.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi4_pipe','../../axi/AXI4/axi4_pipe/axi4_pipe.sv'])
    return_stream = self
    
    slaver = Axi4.same_name_socket(:from_up,mix=true,slaver,nil,belong_to_module) unless slaver.is_a? String
    master = Axi4.same_name_socket(:to_down,mix=true,master,nil,belong_to_module) unless master.is_a? String
    
    if up_stream.nil? && slaver.eql?("slaver") && (!(master.eql?("master")) || !down_stream.nil?)
        # up_stream = self.copy(name:"slaver")
        # return_stream = up_stream
        master = down_stream if down_stream
        return down_stream.axi4_pipe(slaver:self)
    end

    slaver = up_stream if up_stream
    unless self.eql? belong_to_module.Axi4_NC
        master = self
    else
        if down_stream
            master = down_stream
        end
    end


    belong_to_module.Axi4_draw << axi4_pipe_draw(
        slaver:slaver,
        master:master,
        up_stream:up_stream,
        down_stream:down_stream)
    return return_stream
end

#axi4_pipe_draw(slaver: "slaver", master: "master", up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_pipe_auto.rb', line 50

def axi4_pipe_draw(
    slaver:"slaver",
    master:"master",
    up_stream:nil,
    down_stream:nil
)

    large_name_len(
        slaver,
        master
    )
    instance_name = "axi4_pipe_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/axi4_pipe/axi4_pipe.sv
axi4_pipe #{instance_name}(
/*  axi_inf.slaver*/ .slaver (#{align_signal(slaver,q_mark=false)}),
/*  axi_inf.master*/ .master (#{align_signal(master,q_mark=false)})
);
"
end

#axi4_pipe_verb(slaver: "slaver", master: "master", up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_pipe_verb_auto.rb', line 9

def axi4_pipe_verb(
    slaver:"slaver",
    master:"master",
    up_stream:nil,
    down_stream:nil
)

    Tdl.add_to_all_file_paths('axi4_pipe_verb','../../axi/AXI4/axi4_pipe/axi4_pipe_verb.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi4_pipe_verb','../../axi/AXI4/axi4_pipe/axi4_pipe_verb.sv'])
    return_stream = self
    
    slaver = Axi4.same_name_socket(:from_up,mix=true,slaver,nil,belong_to_module) unless slaver.is_a? String
    master = Axi4.same_name_socket(:to_down,mix=true,master,nil,belong_to_module) unless master.is_a? String
    
    if up_stream.nil? && slaver.eql?("slaver") && (!(master.eql?("master")) || !down_stream.nil?)
        # up_stream = self.copy(name:"slaver")
        # return_stream = up_stream
        master = down_stream if down_stream
        return down_stream.axi4_pipe_verb(slaver:self)
    end

    slaver = up_stream if up_stream
    unless self.eql? belong_to_module.Axi4_NC
        master = self
    else
        if down_stream
            master = down_stream
        end
    end


    belong_to_module.Axi4_draw << axi4_pipe_verb_draw(
        slaver:slaver,
        master:master,
        up_stream:up_stream,
        down_stream:down_stream)
    return return_stream
end

#band_params_from(has) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_interconnect_verb.rb', line 44

def band_params_from(has)
    array_list = [:clock,:reset,:dsize,:idsize,:asize,:lsize]
    array_list.each do |e|
        if method(e).call.nil?
            self.send("#{e.to_s}=",has.send(e))
        end
    end
end

#branch(name: nil, clock: @clock, reset: @reset, mode: @mode, dsize: @dsize, idsize: @idsize, asize: @asize, lsize: @lsize, addr_step: @addr_step, dimension: [], freqM: nil) ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 332

def branch(name:@name,clock:@clock,reset:@reset,mode:@mode,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,belong_to_module:@belong_to_module,dimension:[],freqM:nil)
    # puts "freqM :: ",freqM
    a = copy(name:name,clock:clock,reset:reset,mode:mode,dsize:dsize,idsize:idsize,asize:asize,lsize:lsize,addr_step:addr_step,belong_to_module:belong_to_module,dimension:dimension,freqM:freqM)
    self << a
    return a
end

#clock_reset_taps(def_clock_name, def_reset_name) ⇒ Object 



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# File 'lib/tdl/rebuild_ele/axi4.rb', line 141

def clock_reset_taps(def_clock_name,def_reset_name)
    super(def_clock_name,def_reset_name,self.axi_aclk,self.axi_aresetn)
end

#ddr3(app_addr: "app_addr", app_cmd: "app_cmd", app_en: "app_en", app_wdf_data: "app_wdf_data", app_wdf_end: "app_wdf_end", app_wdf_mask: "app_wdf_mask", app_wdf_wren: "app_wdf_wren", app_rd_data: "app_rd_data", app_rd_data_end: "app_rd_data_end", app_rd_data_valid: "app_rd_data_valid", app_rdy: "app_rdy", app_wdf_rdy: "app_wdf_rdy", init_calib_complete: "init_calib_complete") ⇒ Object 



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# File 'lib/tdl/axi4/bak/ddr3.rb', line 7

def ddr3(   app_addr:"app_addr",app_cmd:"app_cmd",app_en:"app_en",app_wdf_data:"app_wdf_data",app_wdf_end:"app_wdf_end",app_wdf_mask:"app_wdf_mask",
            app_wdf_wren:"app_wdf_wren",app_rd_data:"app_rd_data",app_rd_data_end:"app_rd_data_end",
            app_rd_data_valid:"app_rd_data_valid",app_rdy:"app_rdy",app_wdf_rdy:"app_wdf_rdy",init_calib_complete:"init_calib_complete")

    $_draw = lambda { ddr3_draw(axi4_master:self,    app_addr:app_addr,app_cmd:app_cmd,app_en:app_en,app_wdf_data:app_wdf_data,app_wdf_end:app_wdf_end,app_wdf_mask:app_wdf_mask,init_calib_complete:init_calib_complete,
                                    app_wdf_wren:app_wdf_wren,app_rd_data:app_rd_data,app_rd_data_end:app_rd_data_end,app_rd_data_valid:app_rd_data_valid,app_rdy:app_rdy,app_wdf_rdy:app_wdf_rdy) }
    @correlation_proc +=$_draw.call
    return self
end

#ddr3_draw(axi4_master: self, app_addr: nil, app_cmd: nil, app_en: nil, app_wdf_data: nil, app_wdf_end: nil, app_wdf_mask: nil, app_wdf_wren: nil, app_rd_data: nil, app_rd_data_end: nil, app_rd_data_valid: nil, app_rdy: nil, app_wdf_rdy: nil, init_calib_complete: nil) ⇒ Object 



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# File 'lib/tdl/axi4/bak/ddr3.rb', line 17

def ddr3_draw(axi4_master:self,app_addr:nil,app_cmd:nil,app_en:nil,app_wdf_data:nil,app_wdf_end:nil,app_wdf_mask:nil,app_wdf_wren:nil,app_rd_data:nil,app_rd_data_end:nil,app_rd_data_valid:nil,app_rdy:nil,app_wdf_rdy:nil,init_calib_complete:nil)
    large_name_len(axi4_master,app_addr,app_cmd,app_en,app_wdf_data,app_wdf_end,app_wdf_mask,app_wdf_wren,app_rd_data,app_rd_data_end,app_rd_data_valid,app_rdy,app_wdf_rdy,init_calib_complete)
"\naxi4_to_native_for_ddr_ip_verb #(
.ADDR_WIDTH         (#{signal}.ASIZE),
.DATA_WIDTH         (#{signal}.DSIZE)
)axi4_to_native_for_ddr_ip_verb_inst(
/*  axi_inf.slaver                 */ .axi_inf              (#{align_signal(axi4_master          )}),
/*  output logic[ADDR_WIDTH-1:0]   */ .app_addr             (#{align_signal(app_addr             ,false)}),
/*  output logic[2:0]              */ .app_cmd              (#{align_signal(app_cmd              ,false)}),
/*  output logic                   */ .app_en               (#{align_signal(app_en               ,false)}),
/*  output logic[DATA_WIDTH-1:0]   */ .app_wdf_data         (#{align_signal(app_wdf_data         ,false)}),
/*  output logic                   */ .app_wdf_end          (#{align_signal(app_wdf_end          ,false)}),
/*  output logic[DATA_WIDTH/8-1:0] */ .app_wdf_mask         (#{align_signal(app_wdf_mask         ,false)}),
/*  output logic                   */ .app_wdf_wren         (#{align_signal(app_wdf_wren         ,false)}),
/*  input  [DATA_WIDTH-1:0]        */ .app_rd_data          (#{align_signal(app_rd_data          ,false)}),
/*  input                          */ .app_rd_data_end      (#{align_signal(app_rd_data_end      ,false)}),
/*  input                          */ .app_rd_data_valid    (#{align_signal(app_rd_data_valid    ,false)}),
/*  input                          */ .app_rdy              (#{align_signal(app_rdy              ,false)}),
/*  input                          */ .app_wdf_rdy          (#{align_signal(app_wdf_rdy          ,false)}),
/*  input                          */ .init_calib_complete  (#{align_signal(init_calib_complete  ,false)})
);\n"
end

#from_both ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 191

def from_both
    if mode == BOTH
        return self
    end
    # new_obj = Axi4.new(name:@name+"_both",clock:@clock,reset:@reset,mode:Axi4::BOTH,dsize:@dsize,idsize:@idsize,asize:@asize,max_len:@max_len)
    new_obj = belong_to_module.Def.axi4(name:@name+"_both",clock:@clock,reset:@reset,mode:Axi4::BOTH,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,freqM:@origin_freqM)
    new_obj.axi4_direct(down_stream:self)
    return new_obj
end

#from_only_read ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 201

def from_only_read
    if mode == ONLY_READ
        return self
    elsif mode == ONLY_WRITE
        raise TdlError.new("AXI4 can be ONLY_READ to ONLY_WRITE\n")
    end

    # new_obj = Axi4.new(name:@name+"_only_read",clock:@clock,reset:@reset,mode:Axi4::ONLY_READ,dsize:@dsize,idsize:@idsize,asize:@asize,max_len:@max_len)
    new_obj = belong_to_module.Def.axi4(name:@name+"_only_read",clock:@clock,reset:@reset,mode:Axi4::ONLY_READ,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,freqM:@origin_freqM)
    new_obj.axi4_direct(down_stream:self)
    return new_obj
end

#from_only_write ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 214

def from_only_write
    if mode == ONLY_WRITE
        return self
    elsif mode == ONLY_READ
        # Test.puts_sv Axi4.inst
        raise TdlError.new("AXI4 can be ONLY_WRITE to ONLY_READ\n")
    end

    # new_obj = Axi4.new(name:@name+"_only_write",clock:@clock,reset:@reset,mode:Axi4::ONLY_WRITE,dsize:@dsize,idsize:@idsize,asize:@asize,max_len:@max_len)
    new_obj = belong_to_module.Def.axi4(name:@name+"_only_write",clock:@clock,reset:@reset,mode:Axi4::ONLY_WRITE,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,freqM:@origin_freqM)
    new_obj.axi4_direct(down_stream:self)
    return new_obj
end

#from_video(video_slaver: nil, mode: "LINE", base_addr: nil) ⇒ Object 



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# File 'lib/tdl/VideoInf/video_to_axi4.rb', line 53

def from_video(video_slaver:nil,mode:"LINE",base_addr:nil)
    video_slaver.to_axi4(axi4_master:self,mode:mode,base_addr:base_addr)
end

#idata_pool_axi4(dsize: 8, source_addr: "source_addr", size: "size", valid: "valid", ready: "ready", last_drop: "last_drop", data: "data", empty: "empty", wr_en: "wr_en", sewage_valve: "sewage_valve", axi_master: "axi_master", down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/idata_pool_axi4_auto.rb', line 9

def idata_pool_axi4(
    dsize:8,
    source_addr:"source_addr",
    size:"size",
    valid:"valid",
    ready:"ready",
    last_drop:"last_drop",
    data:"data",
    empty:"empty",
    wr_en:"wr_en",
    sewage_valve:"sewage_valve",
    axi_master:"axi_master",
    down_stream:nil
)

    Tdl.add_to_all_file_paths('idata_pool_axi4','../../axi/AXI4/idata_pool_axi4.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['idata_pool_axi4','../../axi/AXI4/idata_pool_axi4.sv'])
    return_stream = self
    
    axi_master = Axi4.same_name_socket(:mirror,mix=true,axi_master,nil,belong_to_module) unless axi_master.is_a? String
    
    
    unless self.eql? belong_to_module.Axi4_NC
        axi_master = self
    else
        if down_stream
            axi_master = down_stream
        end
    end


    belong_to_module.Axi4_draw << idata_pool_axi4_draw(
        dsize:dsize,
        source_addr:source_addr,
        size:size,
        valid:valid,
        ready:ready,
        last_drop:last_drop,
        data:data,
        empty:empty,
        wr_en:wr_en,
        sewage_valve:sewage_valve,
        axi_master:axi_master,
        down_stream:down_stream)
    return return_stream
end

#idata_pool_axi4_draw(dsize: 8, source_addr: "source_addr", size: "size", valid: "valid", ready: "ready", last_drop: "last_drop", data: "data", empty: "empty", wr_en: "wr_en", sewage_valve: "sewage_valve", axi_master: "axi_master", down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi4/idata_pool_axi4_auto.rb', line 58

def idata_pool_axi4_draw(
    dsize:8,
    source_addr:"source_addr",
    size:"size",
    valid:"valid",
    ready:"ready",
    last_drop:"last_drop",
    data:"data",
    empty:"empty",
    wr_en:"wr_en",
    sewage_valve:"sewage_valve",
    axi_master:"axi_master",
    down_stream:nil
)

    large_name_len(
        dsize,
        source_addr,
        size,
        valid,
        ready,
        last_drop,
        data,
        empty,
        wr_en,
        sewage_valve,
        axi_master
    )
    instance_name = "idata_pool_axi4_#{signal}_inst"
"
// FilePath:::../../axi/AXI4/idata_pool_axi4.sv
idata_pool_axi4#(
.DSIZE    (#{align_signal(dsize)})
) #{instance_name}(
/*  input  [31:0]     */ .source_addr  (#{align_signal(source_addr,q_mark=false)}),
/*  input  [31:0]     */ .size         (#{align_signal(size,q_mark=false)}),
/*  input             */ .valid        (#{align_signal(valid,q_mark=false)}),
/*  output            */ .ready        (#{align_signal(ready,q_mark=false)}),
/*  output            */ .last_drop    (#{align_signal(last_drop,q_mark=false)}),
/*  input  [DSIZE-1:0]*/ .data         (#{align_signal(data,q_mark=false)}),
/*  output            */ .empty        (#{align_signal(empty,q_mark=false)}),
/*  input             */ .wr_en        (#{align_signal(wr_en,q_mark=false)}),
/*  input             */ .sewage_valve (#{align_signal(sewage_valve,q_mark=false)}),
/*  axi_inf.master_wr */ .axi_master   (#{align_signal(axi_master,q_mark=false)})
);
"
end

#inherited(name: inst_name, clock: nil, reset: nil, mode: nil, dsize: nil, idsize: nil, asize: nil, lsize: nil, addr_step: nil, dimension: [], freqM: nil) ⇒ Object Also known as: copy 



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# File 'lib/tdl/elements/axi4.rb', line 285

def inherited(name:@name.to_s,
    clock: nil ,
    reset: nil,
    mode:  nil,
    dsize: nil,
    idsize: nil,
    asize: nil,
    lsize: nil,
    addr_step: nil,
    belong_to_module: @belong_to_module,
    dimension: [],
    freqM: nil)

    new_obj = nil 

    ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
        append_name = name_copy(name)
        if clock.nil?
            _clock = self.axi_aclk
        else
            _clock = clock
        end

        _freqM = use_which_freq_when_copy(clock,freqM) || (!(_clock.is_a?( Clock)) && self.FreqM)

        if reset.nil?
            _reset = self.axi_aresetn
        else
            _reset = reset
        end
        new_obj = belong_to_module.Def.axi4(
            name:append_name,
            clock:_clock,
            reset:_reset,
            mode:mode || self.MODE,
            dsize:dsize || self.DSIZE,
            idsize:idsize || self.IDSIZE,
            asize:asize || self.ASIZE,
            lsize:lsize || self.LSIZE,
            addr_step:addr_step || self.ADDR_STEP,
            dimension: dimension ,
            freqM:_freqM)
    end

    return new_obj
end

#inst ⇒ Object

def signal

if @port
    NqString.new(@name.to_s)
else
    NqString.new("axi_#{@name}_#{@id}_inf")
end

end



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# File 'lib/tdl/elements/axi4.rb', line 55

def inst
    return "" if @ghost
    raise TdlError.new "\n #{@name} DSIZE CAN'T BE NIL\n" if @dsize.nil?
    raise TdlError.new "\n #{@name} CLOCK CAN'T BE NIL\n" if @clock.nil?
    raise TdlError.new "\n #{@name} RESET CAN'T BE NIL\n" if @reset.nil?
    raise TdlError.new "\n #{@name} ASIZE CAN'T BE NIL\n" if @asize.nil?
    raise TdlError.new "\n #{@name} IDSIZE CAN'T BE NIL\n" if @idsize.nil?
    raise TdlError.new "\n #{@name} LSIZE CAN'T BE NIL\n" if @lsize.nil?

    large_name_len(@mode,@clock,@reset,addr_step,@mode)
"\naxi_inf #(
.IDSIZE    (#{align_signal(idsize)}),
.ASIZE     (#{align_signal(asize)}),
.LSIZE     (#{align_signal(lsize)}),
.DSIZE     (#{align_signal(dsize)}),
.MODE      (#{align_signal(@mode)}),
.ADDR_STEP (#{align_signal(addr_step,false)}),
.FreqM     (#{freq_align_signal})
)#{signal} #{array_inst}(
.axi_aclk      (#{align_signal(@clock,false)}),
.axi_aresetn   (#{align_signal(@reset.low_signal,false)})
);\n"
end

#inst_port ⇒ Object

def port_length

("axi_inf." + @port.to_s + " ").length

end



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# File 'lib/tdl/elements/axi4.rb', line 83

def inst_port


    # if @port
    #     ("axi_inf." + @port.to_s + " " + " "*sub_len + @name.to_s)
    # end

    return ["axi_inf." + @port.to_s,@name.to_s,array_inst]
end

#interconnect_pipe=(a = false) ⇒ Object

def freeze_min_params(key)

@freeze_min_params_hash ||= Hash.new
@freeze_min_params_hash[key]

end

def freeze_min_params=(key,value)

@freeze_min_params_hash ||= Hash.new
@freeze_min_params_hash[key] = value

end



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# File 'lib/tdl/axi4/axi4_interconnect_verb.rb', line 40

def interconnect_pipe=(a=false)
    @interconnect_pipe=a
end

#old_append(*up_streams) ⇒ Object 



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# File 'lib/tdl/axi4/axi4_interconnect_verb.rb', line 114

def old_append(*up_streams)
    @interconnect_up_streams ||= []
    push_to_stack
    up_streams.each do |e|
        # next unless e.is_a? Axi4
        if e.is_a? Axi4
            e.band_params_from(self)
            
            ## e is a Vector 
            if e.dimension && e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
                # require_hdl 'axi4_direct_B1.sv'
                require_hdl 'axi4_direct_verc.sv'

                e.dimension[0].times do |xi|
                    _ne = e.copy(name: "#{e.inst_name}_toM_#{xi}")
                    # _ne << e[xi]
                    # belong_to_module.Instance('axi4_direct_B1',"axi4_direc_#{e.inst_name}_toM_#{xi}") do |h|
                    #     # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
                    #     h.slaver_inf        e[xi]
                    #     h.master_inf        _ne
                    # end

                    belong_to_module.Instance('axi4_direct_verc',"axi4_direc_#{e.inst_name}_toM_#{xi}") do |h|
                        h.param.MODE            "#{_ne.mode}_to_#{_ne.mode}"    # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
                        h.param.SLAVER_MODE     _ne.mode    #    //
                        h.param.MASTER_MODE     _ne.mode    #    //
                        h.slaver_inf        e[xi]
                        h.master_inf        _ne
                    end
            
                    @interconnect_up_streams << _ne 
                end    
            else
                @interconnect_up_streams << e
            end
        else
            raise TdlError.new("When use `<<` for axi4's M2S ,argvs must be axi4 too.\nOtherwise use `naxi4_mix_interconnect_M2S` directly")
        end
    end
    cal_idsize_asize
    cal_addr_step
end

#sync_mode(up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 228

def sync_mode(up_stream:nil,down_stream:nil)
    if up_stream
        if up_stream.mode == BOTH
            return self.from_both
        elsif up_stream.mode == ONLY_READ
            return self.from_only_read
        elsif up_stream.mode == ONLY_WRITE
            return self.from_only_write
        end
    elsif down_stream
        if down_stream.mode == BOTH
            return self.to_both
        elsif down_stream.mode == ONLY_READ
            return self.to_only_read
        elsif down_stream.mode == ONLY_WRITE
            return self.to_only_write
        end
    end
end

#to_both ⇒ Object

def draw

super
return ''   if @interconnect_up_streams.empty? && @correlation_proc.empty?
head_str = "\n//-------->>>> #{signal} <<<<----------------\n"
end_str  = "\n//========<<<< #{signal} >>>>================\n"
# unless @interconnect_up_streams.empty?
#     @correlation_proc += interconnect_draw
# end
return head_str+@correlation_proc+end_str

end mode trans ============================================================



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# File 'lib/tdl/elements/axi4.rb', line 154

def to_both
    if mode == BOTH
        return self
    end
    # new_obj = Axi4.new(name:@name+"_both",clock:@clock,reset:@reset,mode:Axi4::BOTH,dsize:@dsize,idsize:@idsize,asize:@asize,max_len:@max_len)
    new_obj = belong_to_module.Def.axi4(name:@name+"_both",clock:@clock,reset:@reset,mode:Axi4::BOTH,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,freqM:@origin_freqM)

    new_obj.axi4_direct(up_stream:self)
    return new_obj
end

#to_iillegal_bfm ⇒ Object 



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# File 'lib/tdl/bfm/axi4_illegal_bfm.rb', line 4

def to_iillegal_bfm
    bfm = Axi4IllegalBFM.new(name:"#{@name}_bfm",clock:@clock,reset:@reset,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,mode:@mode,port:false,addr_step: @addr_step,dimension: @dimension)
    bfm.belong_to_module = belong_to_module
    bfm.belong_to_module.var_common(bfm)
    belong_to_module.Axi4_inst  << bfm.inst
    self << bfm
    return bfm
end

#to_only_read ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 165

def to_only_read
    if mode == ONLY_READ
        return self
    elsif mode == ONLY_WRITE
        raise TdlError.new("AXI4 can be ONLY_WRITE to ONLY_READ\n")
    end

    # new_obj = Axi4.new(name:@name+"_only_read",clock:@clock,reset:@reset,mode:Axi4::ONLY_READ,dsize:@dsize,idsize:@idsize,asize:@asize,max_len:@max_len)
    new_obj = belong_to_module.Def.axi4(name:@name+"_only_read",clock:@clock,reset:@reset,mode:Axi4::ONLY_READ,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,freqM:@origin_freqM)
    new_obj.axi4_direct(up_stream:self)
    return new_obj
end

#to_only_write ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 178

def to_only_write
    if mode == ONLY_WRITE
        return self
    elsif mode == ONLY_READ
        raise TdlError.new("AXI4 can be ONLY_READ to ONLY_WRITE\n")
    end

    # new_obj = Axi4.new(name:@name+"_only_write",clock:@clock,reset:@reset,mode:Axi4::ONLY_WRITE,dsize:@dsize,idsize:@idsize,asize:@asize,max_len:@max_len)
    new_obj = belong_to_module.Def.axi4(name:@name+"_only_write",clock:@clock,reset:@reset,mode:Axi4::ONLY_WRITE,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,freqM:@origin_freqM)
    new_obj.axi4_direct(up_stream:self)
    return new_obj
end

#to_video(video_slaver: nil, video_master: nil, mode: "LINE", base_addr: nil) ⇒ Object 



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# File 'lib/tdl/VideoInf/video_from_axi4.rb', line 86

def to_video(video_slaver:nil,video_master:nil,mode:"LINE",base_addr:nil)
    VideoInf.video_from_axi4(axi4_master:self,video_slaver:video_slaver,video_master:video_master,mode:mode,base_addr:base_addr)
end

#vcs_comptable(origin: 'master', to: 'slaver', lock: "origin") ⇒ Object 



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# File 'lib/tdl/elements/axi4.rb', line 620

def vcs_comptable(origin: 'master',to: 'slaver',lock: "origin")

    if belong_to_module.respond_to? "#{@name}_#{origin}_to_#{to}_L#{lock}"
        return belong_to_module.send("#{@name}_#{origin}_to_#{to}_L#{lock}").name.to_nq
    end
    ''' 返回字符串'''
    belong_to_module.instance_exec(self,origin,to,lock) do |origin_inf,origin_modport,to_modport,lock|
        Instance(:vcs_axi4_comptable,"vcs_axi4_comptable_#{origin_inf.name}_#{origin_modport}_#{to_modport}_lock_#{lock}_inst") do |h|
            h[:ORIGIN]  = origin_modport
            h[:TO]      = to_modport
            if lock.to_s.downcase == "origin"
                h[:origin]  = origin_inf
                h[:to]      = origin_inf.copy(name: "#{origin_inf.name}_#{origin_modport}_to_#{to_modport}_L#{lock}")
            else 
                h[:to]      = origin_inf
                h[:origin]  = origin_inf.copy(name: "#{origin_inf.name}_#{origin_modport}_to_#{to_modport}_L#{lock}")
            end
        end
    end

    return belong_to_module.send("#{@name}_#{origin}_to_#{to}_L#{lock}").name.to_nq
end

#video_to_vdma(mode: "LINE", base_addr: "base_addr", video_inf: "video_inf", axi_master: "axi_master", down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi_stream/bak/video_to_VDMA.rb', line 9

def video_to_vdma(mode:"LINE",base_addr:"base_addr",video_inf:"video_inf",axi_master:"axi_master",down_stream:nil)

    axi_master = self

    $_draw = lambda { video_to_vdma_draw(mode:mode,base_addr:base_addr,video_inf:video_inf,axi_master:axi_master,down_stream:down_stream) }
    @correlation_proc += $_draw.call
    return self
end

#video_to_vdma_draw(mode: "LINE", base_addr: "base_addr", video_inf: "video_inf", axi_master: "axi_master", down_stream: nil) ⇒ Object 



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# File 'lib/tdl/axi_stream/bak/video_to_VDMA.rb', line 18

def video_to_vdma_draw(mode:"LINE",base_addr:"base_addr",video_inf:"video_inf",axi_master:"axi_master",down_stream:nil)
    large_name_len(mode,base_addr,video_inf,axi_master)
"
video_to_VDMA#(
.MODE    (#{align_signal(mode)})
) video_to_vdma_#{signal}_inst(
/*  input  [31:0]              */ .base_addr  (#{align_signal(base_addr,q_mark=false)}),
/*  video_native_inf.compact_in*/ .video_inf  (#{align_signal(video_inf,q_mark=false)}),
/*  axi_inf.master             */ .axi_master (#{align_signal(axi_master,q_mark=false)})
);
"
end