Class: TdlSpace::TdlBaseInterface

Inherits:
AxiTdl::SdlModuleActiveBaseElm show all
Extended by:
VarElemenAttr
Includes:
ExCreateTP, VarElemenCore
Defined in:
lib/tdl/exlib/test_point.rb,
lib/tdl/rebuild_ele/ele_base.rb

Direct Known Subclasses

Axi4, AxiLite, AxiStream, CMRamInf, DataInf, DataInf_C, TestAxiStream

Constant Summary collapse

@@child = 
[]

Instance Attribute Summary collapse

Attributes included from VarElemenCore

#dimension, #inst_name, #logic_type

Class Method Summary collapse

Instance Method Summary collapse

Methods included from VarElemenAttr

_io_map, clock_io_map, comm_io_map, comm_io_maps_same, gen_sv_interface, get_class_var, hdl_name, modports, param_map, pdata_map, reset_io_map, sdata_maps, set_class_var

Methods included from VarElemenCore

#[], #_inner_inst, #inst_port, #instance, #modport_type, #modport_type=, #name, #name=, #to_s

Methods included from ExCreateTP

#root_ref

Methods included from AxiTdl::TestUnitTrack

#tracked_by_dve

Constructor Details

#initialize(belong_to_module = nil) ⇒ TdlBaseInterface

Returns a new instance of TdlBaseInterface.



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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 563

def initialize(belong_to_module=nil)
    element_to_module(belong_to_module)
end

Instance Attribute Details

#belong_to_module ⇒ Object

Returns the value of attribute belong_to_module.



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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 561

def belong_to_module
  @belong_to_module
end

Class Method Details

.inherited(subclass) ⇒ Object 



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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 578

def self.inherited(subclass)
    unless @@child.include? subclass
        @@child << subclass
    end
end

.parse_ports(port_array, rep, inf_name, up_stream_rep, type) ⇒ Object 



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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 588

def self.parse_ports(port_array,rep,inf_name,up_stream_rep,type)
    ports = []
    del_ports = []
    if port_array
        ports = port_array.map do |e|
            me = e.match(rep)
            if me
                del_ports << e
                h = Hash.new
                h[:type] = type
                h[:modport] = me["modport"].downcase
    
                if h[:modport]=="master"
                    h[:way] = :to_down
                elsif  h[:modport]=="slaver"
                    h[:way] = :from_up
                else
                    h[:way] = :mirror
                end
    
                h[:name]    = me["name"].downcase
                h[:origin_name] = me["name"]
                h[:vector]  = me["vector"] if me["vector"]
                if me["ud_name"]
                    h[:up_down] = me["ud_name"] =~ up_stream_rep ? "up_stream" : "down_stream"
                else
                    h[:up_down] = "nil"
                end
    
                ##
                port_left_len  = 4+"#{inf_name}.#{h[:modport]}".length+6
                port_right_len = 4+h[:origin_name].length
    
                h[:port_left_len] = port_left_len
                h[:port_right_len] = port_right_len
    
                h[:inst_ex_port] = lambda {|left,right|
                    if left >= port_left_len
                        ll  = left - port_left_len
                    else
                        ll = 1
                    end
    
                    if right >= port_right_len
                        rl  = right - port_right_len
                    else
                        rl = 1
                    end
    
                    "/*  #{inf_name}.#{h[:modport]}" + " "*ll+ "*/ " + ".#{h[:origin_name]}"+" "*rl + " (\#{align_signal(#{h[:name]},q_mark=false)})"
                }
                if block_given?
                    yield h
                end
                ##
                h
            else
                nil
            end
        end
    end
    # puts port_array,"=====",del_ports
    return_ports = port_array - del_ports
    return  return_ports
end

.subclass ⇒ Object 



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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 584

def self.subclass
    @@child
end

Instance Method Details

#clock_reset_taps(def_clock_name, def_reset_name, self_clock, self_reset) ⇒ Object 



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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 701

def clock_reset_taps(def_clock_name,def_reset_name,self_clock,self_reset)

    new_clk = belong_to_module.logic.clock(self.FreqM) - def_clock_name
    new_reset = belong_to_module.logic.reset('low') - def_reset_name
    
    belong_to_module.Assign do 
        new_clk <= self_clock 
        new_reset <= self_reset
    end 
    [new_clk,new_reset]
end

#element_to_module(belong2m) ⇒ Object 



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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 567

def element_to_module(belong2m)
    @belong_to_module = belong2m
    ec = @belong_to_module.instance_variable_get("@__element_collect__") || []
    unless ec.include? self
        ec << self 
        @belong_to_module.instance_variable_set("@__element_collect__",ec)
    end
end

#force_name_copy(nstr) ⇒ Object

Monkey 布丁,



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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 672

def force_name_copy(nstr)
    
    if nstr.to_s.eql?(inst_name.to_s)
        @copy_id ||= 0
        str = "#{nstr.to_s}_copy_#{@copy_id}"
        @copy_id += 1
        str
    else
        nstr.to_s
    end
    
end

#name_copy(nstr) ⇒ Object

Monkey 布丁, 引入一个 StringBandItegration 集成变量



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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 655

def name_copy(nstr)
    nstr = nstr || inst_name
    if nstr.is_a?(StringBandItegration) && true
        return nstr
    else
        if nstr.to_s.eql?(inst_name.to_s)
            @copy_id ||= 0
            str = "#{nstr.to_s}_copy_#{@copy_id}"
            @copy_id += 1
            str
        else
            nstr.to_s
        end
    end
end

#path_refs(&block) ⇒ Object

获取信号的绝对路径



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# File 'lib/tdl/exlib/test_point.rb', line 177

def path_refs(&block)
    collects = []
    if @belong_to_module != TopModule.current.techbench
        @belong_to_module.parents_inst_tree do |tree|
            ll = ["$root"]
            rt = tree.reverse
            rt.each_index do |index|
                if rt[index].respond_to? :module_name
                    ll << rt[index].module_name 
                else 
                    ll << rt[index].inst_name
                end
            end
            ll << inst_name
            new_name = ll.join('.').to_nq
            if block_given?
                if yield(new_name)
                    collects << new_name
                end 
            else
                collects << new_name
            end
        end
    else
        collects = ["$root.#{@belong_to_module.module_name}.#{inst_name}".to_nq]
    end
    collects
end

#use_which_freq_when_copy(argv_clock, argv_origin) ⇒ Object 



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# File 'lib/tdl/rebuild_ele/ele_base.rb', line 685

def use_which_freq_when_copy(argv_clock,argv_origin)
    if argv_clock == @clock && @clock
        if @clock.respond_to? :freqM
            @clock.freqM
        else  
            "#{inst_name}.FreqM".to_nq
        end
    elsif argv_clock != @clock && argv_clock.is_a?(Clock)
        argv_clock.freqM
    elsif !(argv_clock.is_a?(Clock)) && argv_origin
        argv_origin
    else
        nil
    end
end