Class: DataInf

Inherits:
TdlSpace::TdlBaseInterface show all
Extended by:
BaseFunc
Includes:
BaseModule
Defined in:
lib/tdl/elements/data_inf.rb,
lib/tdl/rebuild_ele/data_inf.rb,
lib/tdl/Logic/mdio_model_auto.rb,
lib/tdl/Logic/clock_rst_verb_auto.rb,
lib/tdl/data_inf/common_fifo_auto.rb,
lib/tdl/data_inf/bak/data_inf_planer.rb,
lib/tdl/data_inf/bak/common_fifo_auto.rb,
lib/tdl/data_inf/bak/data_connect_pipe.rb,
lib/tdl/data_inf/bak/data_inf_ticktack.rb,
lib/tdl/data_inf/bak/data_inf_cross_clk.rb,
lib/tdl/data_inf/bak/data_inf_interconnect.rb,
lib/tdl/data_inf/datainf_master_empty_auto.rb,
lib/tdl/data_inf/datainf_slaver_empty_auto.rb,
lib/tdl/data_inf/independent_clock_fifo_auto.rb,
lib/tdl/data_inf/bak/datainf_master_empty_auto.rb,
lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb,
lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb,
lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb,
lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb

Overview

2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative ‘....tdltdl’

Constant Summary collapse

Synth_REP =

parse text for autogen method and constant ###

Regexp.union(/\(\*\s+datainf\s*=\s*"true"\s+\*\)/, /\(\*\s+data_inf\s*=\s*"true"\s+\*\)/)
PORT_REP = 
/(?<up_down>\(\*\s+(?<ud_name>data_up|data_down|up_stream|down_stream)\s*=\s*"true"\s+\*\))?\s*(data_inf\.)(?<modport>master|slaver|mirror)\s+(?<name>\w+)\s*(?<vector>\[.*?\])?/m
UP_STREAM_REP = 
/data_up/

Instance Attribute Summary collapse

Attributes inherited from TdlSpace::TdlBaseInterface

#belong_to_module

Attributes included from TdlSpace::VarElemenCore

#dimension, #inst_name, #logic_type

Class Method Summary collapse

Instance Method Summary collapse

Methods included from BaseFunc

check_same, check_same_class, check_same_clock, check_same_dsize

Methods included from BaseModule

#length, #to_s

Methods inherited from TdlSpace::TdlBaseInterface

#clock_reset_taps, #element_to_module, #force_name_copy, inherited, #name_copy, #path_refs, subclass, #use_which_freq_when_copy

Methods included from TdlSpace::VarElemenAttr

#_io_map, #clock_io_map, #comm_io_map, #comm_io_maps_same, #gen_sv_interface, #get_class_var, #hdl_name, #modports, #param_map, #pdata_map, #reset_io_map, #sdata_maps, #set_class_var

Methods included from TdlSpace::VarElemenCore

#[], #_inner_inst, #instance, #modport_type, #modport_type=, #to_s

Methods included from TdlSpace::ExCreateTP

#root_ref

Methods included from AxiTdl::TestUnitTrack

#tracked_by_dve

Constructor Details

#initialize(name: "data_inf", dsize: 8, port: false, dimension: []) ⇒ DataInf

Returns a new instance of DataInf.



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# File 'lib/tdl/elements/data_inf.rb', line 11

def initialize(name:"data_inf",dsize:8,port:false,dimension:[])
    name_legal?(name)
    super()
    @port = port
    @dsize = dsize
    @name = name
    # @id = GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.id

    # @correlation_proc = ""
    @_to_data_inf_c = ""
    # if @port
    #     GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.ports << self
    # else
    #     GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.inst_stack << method(:inst).to_proc
    # end
    @interconnect_up_streams = []
    @interconnect_idsize = 1
    # GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.draw_stack << method(:draw).to_proc
end

Instance Attribute Details

#dsize ⇒ Object

<tdl_key><hdl_key><default_value>



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# File 'lib/tdl/rebuild_ele/data_inf.rb', line 6

def dsize
  @dsize
end

#ghost ⇒ Object

Returns the value of attribute ghost.



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# File 'lib/tdl/elements/data_inf.rb', line 10

def ghost
  @ghost
end

#id ⇒ Object

Returns the value of attribute id.



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# File 'lib/tdl/elements/data_inf.rb', line 10

def id
  @id
end

#interconnect_mid ⇒ Object

Returns the value of attribute interconnect_mid.



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# File 'lib/tdl/data_inf/bak/data_inf_interconnect.rb', line 5

def interconnect_mid
  @interconnect_mid
end

#name ⇒ Object

Returns the value of attribute name.



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# File 'lib/tdl/elements/data_inf.rb', line 10

def name
  @name
end

#port ⇒ Object

Returns the value of attribute port.



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# File 'lib/tdl/elements/data_inf.rb', line 10

def port
  @port
end

Class Method Details

.clock_rst_verb(active: 1, period_cnt: 0, rst_hold: 5, freqm: 100, clock: "clock", rst_x: "rst_x", belong_to_module: nil) ⇒ Object 



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# File 'lib/tdl/Logic/clock_rst_verb_auto.rb', line 74

def self.clock_rst_verb(
    active:1,
    period_cnt:0,
    rst_hold:5,
    freqm:100,
    clock:"clock",
    rst_x:"rst_x",
    belong_to_module:nil
    )
    return_stream = nil
    
    
    
    belong_to_module.DataInf_NC._clock_rst_verb(
        active:active,
        period_cnt:period_cnt,
        rst_hold:rst_hold,
        freqm:freqm,
        clock:clock,
        rst_x:rst_x)
    return return_stream
end

.common_fifo(depth: 4, dsize: 8, clock: "clock", rst_n: "rst_n", wdata: "wdata", wr_en: "wr_en", rdata: "rdata", rd_en: "rd_en", count: "count", empty: "empty", full: "full") ⇒ Object 



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# File 'lib/tdl/data_inf/common_fifo_auto.rb', line 104

def self.common_fifo(
    depth:4,
    dsize:8,
    csize:NqString.new('$clog2(DEPTH+1)'),
    clock:"clock",
    rst_n:"rst_n",
    wdata:"wdata",
    wr_en:"wr_en",
    rdata:"rdata",
    rd_en:"rd_en",
    count:"count",
    empty:"empty",
    full:"full",
    belong_to_module:nil
    )
    return_stream = nil
    
    
    
    belong_to_module.DataInf_NC._common_fifo(
        depth:depth,
        dsize:dsize,
        csize:csize,
        clock:clock,
        rst_n:rst_n,
        wdata:wdata,
        wr_en:wr_en,
        rdata:rdata,
        rd_en:rd_en,
        count:count,
        empty:empty,
        full:full)
    return return_stream
end

.datainf_master_empty(master: "master", down_stream: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/datainf_master_empty_auto.rb', line 57

def self.datainf_master_empty(
    master:"master",
    down_stream:nil,
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [master].first.belong_to_module unless belong_to_module
    
    
    
    if down_stream.is_a? DataInf
        down_stream.datainf_master_empty(
            master:master,
            down_stream:down_stream)
    elsif master.is_a? DataInf
        master.datainf_master_empty(
            master:master,
            down_stream:down_stream)
    else
        belong_to_module.DataInf_NC.datainf_master_empty(
            master:master,
            down_stream:down_stream)
    end
    return return_stream
end

.datainf_slaver_empty(slaver: "slaver", up_stream: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/datainf_slaver_empty_auto.rb', line 51

def self.datainf_slaver_empty(
    slaver:"slaver",
    up_stream:nil,
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [slaver].first.belong_to_module unless belong_to_module
    
    
    belong_to_module.DataInf_NC._datainf_slaver_empty(
        slaver:slaver,
        up_stream:up_stream)
    return return_stream
end

.independent_clock_fifo(depth: 4, dsize: 8, wr_clk: "wr_clk", wr_rst_n: "wr_rst_n", rd_clk: "rd_clk", rd_rst_n: "rd_rst_n", wdata: "wdata", wr_en: "wr_en", rdata: "rdata", rd_en: "rd_en", empty: "empty", full: "full") ⇒ Object 



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# File 'lib/tdl/data_inf/independent_clock_fifo_auto.rb', line 104

def self.independent_clock_fifo(
    depth:4,
    dsize:8,
    wr_clk:"wr_clk",
    wr_rst_n:"wr_rst_n",
    rd_clk:"rd_clk",
    rd_rst_n:"rd_rst_n",
    wdata:"wdata",
    wr_en:"wr_en",
    rdata:"rdata",
    rd_en:"rd_en",
    empty:"empty",
    full:"full",
    belong_to_module:nil
    )
    return_stream = nil
    
    
    
    belong_to_module.DataInf_NC._independent_clock_fifo(
        depth:depth,
        dsize:dsize,
        wr_clk:wr_clk,
        wr_rst_n:wr_rst_n,
        rd_clk:rd_clk,
        rd_rst_n:rd_rst_n,
        wdata:wdata,
        wr_en:wr_en,
        rdata:rdata,
        rd_en:rd_en,
        empty:empty,
        full:full)
    return return_stream
end

.master_empty(*ms) ⇒ Object

def self.NC

GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.nc

end

def self.nc_create

DataInf.new(name:"implicit",dsize:1)

end



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# File 'lib/tdl/elements/data_inf.rb', line 152

def self.master_empty(*ms)
    ms.each do |e|
        self.datainf_master_empty(master:e)
    end
end

.mdio_model(reset: "reset", mdio: "mdio", mdc: "mdc", belong_to_module: nil) ⇒ Object 



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# File 'lib/tdl/Logic/mdio_model_auto.rb', line 58

def self.mdio_model(
    reset:"reset",
    mdio:"mdio",
    mdc:"mdc",
    belong_to_module:nil
    )
    return_stream = nil
    
    
    
    belong_to_module.DataInf_NC._mdio_model(
        reset:reset,
        mdio:mdio,
        mdc:mdc)
    return return_stream
end

.parse_ports(port_array = nil) ⇒ Object 



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# File 'lib/tdl/elements/data_inf.rb', line 179

def self.parse_ports(port_array=nil)
    rep = /(?<up_down>\(\*\s+(?<ud_name>data_up|data_down|up_stream|down_stream)\s*=\s*"true"\s+\*\))?\s*(data_inf\.)(?<modport>master|slaver|mirror)\s+(?<name>\w+)\s*(?<vector>\[.*?\])?/m
    up_stream_rep = /data_up/

    InfElm.parse_ports(port_array,rep,"data_inf",up_stream_rep) do |h|
        h[:type]   = DataInf
        yield h
    end
end

.slaver_empty(*ss) ⇒ Object 



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# File 'lib/tdl/elements/data_inf.rb', line 158

def self.slaver_empty(*ss)
    ss.each do |e|
        self.datainf_slaver_empty(slaver:e)
    end
end

Instance Method Details

#<<(*up_streams) ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_inf_interconnect.rb', line 6

def <<(*up_streams)
    unless @interconnect_up_streams.empty?
        suit_type  = @interconnect_up_streams.first
    else
        suit_type   = up_streams.reject { |e| (e.is_a? Clock) || (e.is_a? Reset) || (e.is_a? DataInf_C)}.first
        suit_type   = self unless suit_type
    end

    up_streams.each do |e|
        if (e.is_a? DataInf) || (e.is_a? DataInf_C)
            if (suit_type.is_a? DataInf)
                if e.is_a? DataInf_C
                    @interconnect_up_streams << e.to_data_inf()
                else
                    @interconnect_up_streams << e
                end
            else
                raise TdlError.new("DATA INF INTERCONNECT UP_STREAMS ERROR")
            end
        elsif e.is_a? Hash
            if suit_type.is_a? Hash
                if e[:inf].is_a? DataInf_C
                    @interconnect_up_streams << {:inf=>e[:inf].to_data_inf(),:id=>e[:id]}
                else
                    @interconnect_up_streams << e
                end
                @interconnect_idsize  = e[:id].dsize if e[:id].dsize > @interconnect_idsize
            else
                raise TdlError.new("DATA INF INTERCONNECT UP_STREAMS ERROR")
            end
        elsif e.is_a? Clock
            @interconnect_clock = e
        elsif e.is_a? Reset
            if e.active != 'low'
                @interconnect_reset = "~"+e.signal
            else
                @interconnect_reset = e
            end
        else
            raise TdlError.new("DATA INF INTERCONNECT UP_STREAMS ERROR")
        end
    end
end

#_clock_rst_verb(active: 1, period_cnt: 0, rst_hold: 5, freqm: 100, clock: "clock", rst_x: "rst_x") ⇒ Object 



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# File 'lib/tdl/Logic/clock_rst_verb_auto.rb', line 9

def _clock_rst_verb(
    active:1,
    period_cnt:0,
    rst_hold:5,
    freqm:100,
    clock:"clock",
    rst_x:"rst_x"
)

    Tdl.add_to_all_file_paths('clock_rst_verb','../../github/public_atom_modules/sim/clock_rst_verb.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['clock_rst_verb','../../github/public_atom_modules/sim/clock_rst_verb.sv'])
    return_stream = self
    

    
    
    


    belong_to_module.DataInf_draw << _clock_rst_verb_draw(
        active:active,
        period_cnt:period_cnt,
        rst_hold:rst_hold,
        freqm:freqm,
        clock:clock,
        rst_x:rst_x)
    return return_stream
end

#_common_fifo(depth: 4, dsize: 8, clock: "clock", rst_n: "rst_n", wdata: "wdata", wr_en: "wr_en", rdata: "rdata", rd_en: "rd_en", count: "count", empty: "empty", full: "full") ⇒ Object 



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# File 'lib/tdl/data_inf/common_fifo_auto.rb', line 9

def _common_fifo(
    depth:4,
    dsize:8,
    csize:NqString.new('$clog2(DEPTH+1)'),
    clock:"clock",
    rst_n:"rst_n",
    wdata:"wdata",
    wr_en:"wr_en",
    rdata:"rdata",
    rd_en:"rd_en",
    count:"count",
    empty:"empty",
    full:"full"
)

    Tdl.add_to_all_file_paths('common_fifo','../../axi/common_fifo/common_fifo.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['common_fifo','../../axi/common_fifo/common_fifo.sv'])
    return_stream = self
    

    
    
    


    belong_to_module.DataInf_draw << _common_fifo_draw(
        depth:depth,
        dsize:dsize,
        csize:csize,
        clock:clock,
        rst_n:rst_n,
        wdata:wdata,
        wr_en:wr_en,
        rdata:rdata,
        rd_en:rd_en,
        count:count,
        empty:empty,
        full:full)
    return return_stream
end

#_common_fifo_draw(depth: 4, dsize: 8, clock: "clock", rst_n: "rst_n", wdata: "wdata", wr_en: "wr_en", rdata: "rdata", rd_en: "rd_en", count: "count", empty: "empty", full: "full") ⇒ Object 



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# File 'lib/tdl/data_inf/common_fifo_auto.rb', line 52

def _common_fifo_draw(
    depth:4,
    dsize:8,
    csize:NqString.new('$clog2(DEPTH+1)'),
    clock:"clock",
    rst_n:"rst_n",
    wdata:"wdata",
    wr_en:"wr_en",
    rdata:"rdata",
    rd_en:"rd_en",
    count:"count",
    empty:"empty",
    full:"full"
)

    large_name_len(
        depth,
        dsize,
        csize,
        clock,
        rst_n,
        wdata,
        wr_en,
        rdata,
        rd_en,
        count,
        empty,
        full
    )
    instance_name = "common_fifo_#{signal}_inst"
"
// FilePath:::../../axi/common_fifo/common_fifo.sv
common_fifo#(
.DEPTH    (#{align_signal(depth)}),
.DSIZE    (#{align_signal(dsize)}),
.CSIZE    (#{align_signal(csize)})
) #{instance_name}(
/*  input             */ .clock (#{align_signal(clock,q_mark=false)}),
/*  input             */ .rst_n (#{align_signal(rst_n,q_mark=false)}),
/*  input  [DSIZE-1:0]*/ .wdata (#{align_signal(wdata,q_mark=false)}),
/*  input             */ .wr_en (#{align_signal(wr_en,q_mark=false)}),
/*  output [DSIZE-1:0]*/ .rdata (#{align_signal(rdata,q_mark=false)}),
/*  input             */ .rd_en (#{align_signal(rd_en,q_mark=false)}),
/*  output [CSIZE-1:0]*/ .count (#{align_signal(count,q_mark=false)}),
/*  output            */ .empty (#{align_signal(empty,q_mark=false)}),
/*  output            */ .full  (#{align_signal(full,q_mark=false)})
);
"
end

#_datainf_slaver_empty(slaver: "slaver", up_stream: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/datainf_slaver_empty_auto.rb', line 9

def _datainf_slaver_empty(
    slaver:"slaver",
    up_stream:nil
)

    Tdl.add_to_all_file_paths('datainf_slaver_empty','../../axi/data_interface/datainf_slaver_empty.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['datainf_slaver_empty','../../axi/data_interface/datainf_slaver_empty.sv'])
    return_stream = self
    
    slaver = DataInf.same_name_socket(:from_up,mix=true,slaver,nil,belong_to_module) unless slaver.is_a? String
    
    slaver = up_stream if up_stream
    


    belong_to_module.DataInf_draw << _datainf_slaver_empty_draw(
        slaver:slaver,
        up_stream:up_stream)
    return return_stream
end

#_datainf_slaver_empty_draw(slaver: "slaver", up_stream: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/datainf_slaver_empty_auto.rb', line 32

def _datainf_slaver_empty_draw(
    slaver:"slaver",
    up_stream:nil
)

    large_name_len(
        slaver
    )
    instance_name = "datainf_slaver_empty_#{signal}_inst"
"
// FilePath:::../../axi/data_interface/datainf_slaver_empty.sv
datainf_slaver_empty #{instance_name}(
/*  data_inf.slaver*/ .slaver (#{align_signal(slaver,q_mark=false)})
);
"
end

#_independent_clock_fifo(depth: 4, dsize: 8, wr_clk: "wr_clk", wr_rst_n: "wr_rst_n", rd_clk: "rd_clk", rd_rst_n: "rd_rst_n", wdata: "wdata", wr_en: "wr_en", rdata: "rdata", rd_en: "rd_en", empty: "empty", full: "full") ⇒ Object 



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# File 'lib/tdl/data_inf/independent_clock_fifo_auto.rb', line 9

def _independent_clock_fifo(
    depth:4,
    dsize:8,
    wr_clk:"wr_clk",
    wr_rst_n:"wr_rst_n",
    rd_clk:"rd_clk",
    rd_rst_n:"rd_rst_n",
    wdata:"wdata",
    wr_en:"wr_en",
    rdata:"rdata",
    rd_en:"rd_en",
    empty:"empty",
    full:"full"
)

    Tdl.add_to_all_file_paths('independent_clock_fifo','../../axi/common_fifo/independent_clock_fifo.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['independent_clock_fifo','../../axi/common_fifo/independent_clock_fifo.sv'])
    return_stream = self
    

    
    
    


    belong_to_module.DataInf_draw << _independent_clock_fifo_draw(
        depth:depth,
        dsize:dsize,
        wr_clk:wr_clk,
        wr_rst_n:wr_rst_n,
        rd_clk:rd_clk,
        rd_rst_n:rd_rst_n,
        wdata:wdata,
        wr_en:wr_en,
        rdata:rdata,
        rd_en:rd_en,
        empty:empty,
        full:full)
    return return_stream
end

#_independent_clock_fifo_draw(depth: 4, dsize: 8, wr_clk: "wr_clk", wr_rst_n: "wr_rst_n", rd_clk: "rd_clk", rd_rst_n: "rd_rst_n", wdata: "wdata", wr_en: "wr_en", rdata: "rdata", rd_en: "rd_en", empty: "empty", full: "full") ⇒ Object 



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# File 'lib/tdl/data_inf/independent_clock_fifo_auto.rb', line 52

def _independent_clock_fifo_draw(
    depth:4,
    dsize:8,
    wr_clk:"wr_clk",
    wr_rst_n:"wr_rst_n",
    rd_clk:"rd_clk",
    rd_rst_n:"rd_rst_n",
    wdata:"wdata",
    wr_en:"wr_en",
    rdata:"rdata",
    rd_en:"rd_en",
    empty:"empty",
    full:"full"
)

    large_name_len(
        depth,
        dsize,
        wr_clk,
        wr_rst_n,
        rd_clk,
        rd_rst_n,
        wdata,
        wr_en,
        rdata,
        rd_en,
        empty,
        full
    )
    instance_name = "independent_clock_fifo_#{signal}_inst"
"
// FilePath:::../../axi/common_fifo/independent_clock_fifo.sv
independent_clock_fifo#(
.DEPTH    (#{align_signal(depth)}),
.DSIZE    (#{align_signal(dsize)})
) #{instance_name}(
/*  input             */ .wr_clk   (#{align_signal(wr_clk,q_mark=false)}),
/*  input             */ .wr_rst_n (#{align_signal(wr_rst_n,q_mark=false)}),
/*  input             */ .rd_clk   (#{align_signal(rd_clk,q_mark=false)}),
/*  input             */ .rd_rst_n (#{align_signal(rd_rst_n,q_mark=false)}),
/*  input  [DSIZE-1:0]*/ .wdata    (#{align_signal(wdata,q_mark=false)}),
/*  input             */ .wr_en    (#{align_signal(wr_en,q_mark=false)}),
/*  output [DSIZE-1:0]*/ .rdata    (#{align_signal(rdata,q_mark=false)}),
/*  input             */ .rd_en    (#{align_signal(rd_en,q_mark=false)}),
/*  output            */ .empty    (#{align_signal(empty,q_mark=false)}),
/*  output            */ .full     (#{align_signal(full,q_mark=false)})
);
"
end

#_mdio_model(reset: "reset", mdio: "mdio", mdc: "mdc") ⇒ Object 



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# File 'lib/tdl/Logic/mdio_model_auto.rb', line 9

def _mdio_model(
    reset:"reset",
    mdio:"mdio",
    mdc:"mdc"
)

    Tdl.add_to_all_file_paths('mdio_model','../../repository/ethernet_protocol/model/mdio_model.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['mdio_model','../../repository/ethernet_protocol/model/mdio_model.sv'])
    return_stream = self
    

    
    
    


    belong_to_module.DataInf_draw << _mdio_model_draw(
        reset:reset,
        mdio:mdio,
        mdc:mdc)
    return return_stream
end

#a_interconnect_draw(prio: "OFF") ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_inf_interconnect.rb', line 81

def a_interconnect_draw(prio:"OFF")
    clock = @interconnect_clock
    reset = @interconnect_reset
    num = @interconnect_up_streams.length
    large_name_len(num,prio,clock,reset,"sub_#{signal}")
    sub_inst +
"data_inf_interconnect_M2S_noaddr #(
.NUM    (#{align_signal(num)}),
.PRIO   (#{align_signal(prio)})
)data_inf_interconnect_M2S_noaddr_#{signal}_inst(
/*  input           */ .clock       (#{align_signal(clock)}),
/*  input           */ .rst_n       (#{align_signal(reset)}),
/*  data_inf.slaver */ .s00         (#{align_signal("sub_#{signal}",false)}),//[NUM-1:0],
/*  data_inf.master */ .m00         (#{align_signal(self)})
);"
end

#b_interconnect_draw(prio: "OFF") ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_inf_interconnect.rb', line 98

def b_interconnect_draw(prio:"OFF")
    idsize= @interconnect_idsize
    clock = @interconnect_clock
    reset = @interconnect_reset
    num = @interconnect_up_streams.length
    large_name_len(num,prio,clock,reset,"sub_#{signal}",@interconnect_mid)
    sub_inst +
"data_inf_interconnect_M2S_with_id_noaddr #(
.NUM    (#{align_signal(num)}),
.IDSIZE (#{align_signal(idsize)}),
.PRIO   (#{align_signal(prio)})
)data_inf_interconnect_M2S_with_id_noaddr_#{signal}_inst(
/*  input              */ .clock       (#{align_signal(clock)}),
/*  input              */ .rst_n       (#{align_signal(reset)}),
/*  input [IDSIZE-1:0] */ .sid         (#{align_signal("#{signal}_sid",false)})//[NUM-1:0],
/*  output[IDSIZE-1:0] */ .mid         (#{align_signal(@interconnect_mid)})//,
/*  data_inf.slaver    */ .s00         (#{align_signal("sub_#{signal}",false)}),//[NUM-1:0],
/*  data_inf.master    */ .m00         (#{align_signal(self)})
);"
end

#branch(name: @name, dsize: @dsize) ⇒ Object 



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# File 'lib/tdl/elements/data_inf.rb', line 169

def branch(name:@name,dsize:@dsize)
    a =  copy(name:name,dsize:dsize)
    self << a
    return a
end

#copy(name: @name.to_s, dsize: "#{signal}.DSIZE") ⇒ Object 



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# File 'lib/tdl/elements/data_inf.rb', line 164

def copy(name:@name.to_s,dsize:"#{signal}.DSIZE")
    append_name = name_copy(name)
    belong_to_module.Def.datainf(name:append_name,dsize:dsize)
end

#data_connect_pipe(clock: nil, reset: nil, up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_connect_pipe.rb', line 49

def data_connect_pipe(clock:nil,reset:nil,up_stream:nil,down_stream:nil)
    if down_stream && !up_stream
        down_stream.data_connect_pipe(clock:clock,reset:reset,up_stream:self,down_stream:nil)
        return down_stream
    end

    down_stream = self

    if up_stream.is_a? DataInf
        up_stream_c = up_stream.to_data_inf_c(clock:clock,reset:reset)
    else
        up_stream_c = up_stream
    end
    down_stream_c = self.from_data_inf_c(clock:clock,reset:reset)
    down_stream_c.data_connect_pipe(up_stream:up_stream_c)
    return up_stream
end

#data_inf_cross_clk(clock: nil, reset: nil, up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_inf_cross_clk.rb', line 30

def data_inf_cross_clk(clock:nil,reset:nil,up_stream:nil,down_stream:nil)
    if down_stream && !up_stream
        down_stream.data_inf_cross_clk(up_stream:self,down_stream:down_stream,clock:clock,reset:reset)
        return down_stream
    end

    down_stream = self

    down_stream.from_data_inf_c(clock:clock,reset:reset).data_inf_cross_clk(up_stream:up_stream.to_data_inf_c(clock:clock,reset:reset))

    return up_stream

end

#data_inf_planer(latency: 3, clock: nil, reset: nil, pack_data: nil, up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_inf_planer.rb', line 7

def data_inf_planer(latency:3,clock:nil,reset:nil,pack_data:nil,up_stream:nil,down_stream:nil)
    if down_stream && !up_stream
        down_stream.data_inf_planer(latency:latency,clock:clock,reset:reset,pack_data:pack_data,up_stream:self,down_stream:down_stream)
        return down_stream
    end

    down_stream = self

    if (reset.is_a? Reset) && (reset.active != 'low')
        reset_str = "~"+reset.signal
    else
        reset_str = reset;
    end

    $_draw = lambda { data_inf_planer_draw(latency:latency,clock:clock,reset:reset_str,pack_data:pack_data,up_stream:up_stream,down_stream:down_stream) }
    @correlation_proc +=$_draw.call
    return self
end

#data_inf_planer_draw(latency: 3, clock: nil, reset: nil, pack_data: nil, up_stream: nil, down_stream: self) ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_inf_planer.rb', line 27

def data_inf_planer_draw(latency:3,clock:nil,reset:nil,pack_data:nil,up_stream:nil,down_stream:self)
    large_name_len(latency,"#{signal}.DSIZE",up_stream,down_stream)
"data_inf_planer #(
.LAT        (#{align_signal(latency)}),
.DSIZE      (#{align_signal("#{signal}.DSIZE",false)})
)data_inf_planer_#{signal}_inst(
/*  input            */   .clock        (#{align_signal(clock)}),
/*  input            */   .rst_n        (#{align_signal(reset)}),
/*  input [DSIZE-1:0]*/   .pack_data    (#{align_signal(pack_data)}),
/*  data_inf.slaver  */   .slaver       (#{align_signal(up_stream)}),
/*  data_inf.master  */   .master       (#{align_signal(down_stream)})            //{pack_data,slaver.data}
);"
end

#data_inf_ticktack(sub_hbit: @dsize-1, sub_lbit: 0, mode: "COMPARE:<", index_data: nil, compare_data: nil, up_stream: nil, down_stream: self, clock: nil, reset: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_inf_ticktack.rb', line 6

def data_inf_ticktack(sub_hbit:@dsize-1,sub_lbit:0,mode:"COMPARE:<",index_data:nil,compare_data:nil,up_stream:nil,down_stream:self,clock:nil,reset:nil)
    if down_stream && !up_stream
        down_stream.data_inf_planer(sub_hbit:sub_hbit,sub_lbit:sub_lbit,mode:mode,index_data:index_data,compare_data:compare_data,up_stream:self,down_stream:down_stream,clock:clock,reset:reset)
        return down_stream
    end

    down_stream = self

    if (reset.is_a? Reset) && (reset.active != 'low')
        reset_str = "~"+reset.signal
    else
        reset_str = reset;
    end

    $_draw = lambda { data_inf_ticktack_draw(sub_hbit:sub_hbit,sub_lbit:sub_lbit,mode:mode,index_data:index_data,compare_data:compare_data,up_stream:self,down_stream:down_stream,clock:clock,reset:reset_str) }
    @correlation_proc +=$_draw.call
    return self
end

#data_inf_ticktack_draw(sub_hbit: @dsize-1, sub_lbit: 0, mode: "COMPARE:<", index_data: nil, compare_data: nil, up_stream: nil, down_stream: self, clock: nil, reset: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_inf_ticktack.rb', line 26

def data_inf_ticktack_draw(sub_hbit:@dsize-1,sub_lbit:0,mode:"COMPARE:<",index_data:nil,compare_data:nil,up_stream:nil,down_stream:self,clock:nil,reset:nil)
    large_name_len(sub_hbit,sub_lbit,mode,index_data,compare_data,up_stream,down_stream,clock,reset)
"data_inf_ticktack #(
.DSIZE      (#{signal}.DSIZE),
.SUB_HBIT   (#{align_signal(sub_hbit)}),
.SUB_LBIT   (#{align_signal(sub_lbit)}),
.MODE       (#{align_signal(mode)}), //COMPARE:< COMPARE:> COMPARE:<= COMPARE:>= COMPARE:== COMPARE:!= ,INDEX
.ISIZE      (#{align_signal(index_data.dsize)})        // ONLY INDEX MODE
)data_inf_ticktack_#{signal}_inst(
/*  input             */  .clock        (#{align_signal(clock)}),
/*  input             */  .rst_n        (#{align_signal(reset)}),
/*  input [DSIZE-1:0] */  .compare_data (#{align_signal(compare_data)}),
/*  input [ISIZE-1:0] */  .index_data   (#{align_signal(index_data)}),
/*  data_inf.slaver   */  .slaver       (#{align_signal(up_stream)}),
/*  data_inf.master   */  .master       (#{align_signal(down_stream)})
);"
end

#datainf_master_empty(master: "master", down_stream: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/datainf_master_empty_auto.rb', line 9

def datainf_master_empty(
    master:"master",
    down_stream:nil
)

    Tdl.add_to_all_file_paths('datainf_master_empty','../../axi/data_interface/datainf_master_empty.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['datainf_master_empty','../../axi/data_interface/datainf_master_empty.sv'])
    return_stream = self
    
    master = DataInf.same_name_socket(:to_down,mix=true,master,nil,belong_to_module) unless master.is_a? String
    
    
    unless self.eql? belong_to_module.DataInf_NC
        master = self
    else
        if down_stream
            master = down_stream
        end
    end


    belong_to_module.DataInf_draw << datainf_master_empty_draw(
        master:master,
        down_stream:down_stream)
    return return_stream
end

#datainf_master_empty_draw(master: "master", down_stream: nil) ⇒ Object 



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# File 'lib/tdl/data_inf/datainf_master_empty_auto.rb', line 38

def datainf_master_empty_draw(
    master:"master",
    down_stream:nil
)

    large_name_len(
        master
    )
    instance_name = "datainf_master_empty_#{signal}_inst"
"
// FilePath:::../../axi/data_interface/datainf_master_empty.sv
datainf_master_empty #{instance_name}(
/*  data_inf.master*/ .master (#{align_signal(master,q_mark=false)})
);
"
end

#from_data_inf_c(clock: nil, reset: nil) ⇒ Object 



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# File 'lib/tdl/elements/data_inf.rb', line 110

def from_data_inf_c(clock:nil,reset:nil)
    new_obj = belong_to_module.Def.datainf_c(name:@name+"_c",clock:clock,reset:reset,dsize:@dsize)
    belong_to_module.DataInf_C_draw << from_data_inf_c_draw(up_stream:new_obj,down_stream:self)
    return new_obj
end

#from_data_inf_c_draw(up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/elements/data_inf.rb', line 116

def from_data_inf_c_draw(up_stream:nil,down_stream:nil)
    large_name_len(up_stream,down_stream)
"data_inf_B2A data_inf_B2A_#{signal}_inst (
/*  data_inf_c.slaver */  .slaver   (#{align_signal(up_stream)}),
/*  data_inf.master   */  .master   (#{align_signal(down_stream)})
);"
end

#inst ⇒ Object

def signal

if @port
    NqString.new(@name.to_s)
else
    # "data_#{name}_#{@id}_inf"
    NqString.new("#{@name}_#{@id}_inf")
end

end



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# File 'lib/tdl/elements/data_inf.rb', line 40

def inst
    return "" if @ghost
    "data_inf #(.DSIZE(#{dsize.abs}))  #{signal} ();"
end

#inst_port ⇒ Object

def port_length

("data_inf." + @port.to_s + " ").length

end



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# File 'lib/tdl/elements/data_inf.rb', line 49

def inst_port

    # if @port
    #     ("data_inf." + @port.to_s + " " + " "*sub_len + @name.to_s)
    # end
    return ["data_inf." + @port.to_s,@name.to_s,array_inst]
end

#sub_direct ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_inf_interconnect.rb', line 61

def sub_direct
    str = ""
    for i in 0...(@interconnect_up_streams.length)
        if @interconnect_up_streams[i].is_a? DataInf
            up_stream   = @interconnect_up_streams[i]
        else
            up_stream   = @interconnect_up_streams[i][:inf]
            sid = @interconnect_up_streams[i][:id]
        end
        str +=
"
#{sid ? "assign #{signal}_sid[#{i}]  = #{sid.signal};" : ""}
assign sub_#{signal}[#{i}].valid        = #{up_stream.signal}.valid;
assign sub_#{signal}[#{i}].data         = #{up_stream.signal}.data;
assign #{up_stream.signal}.ready     = sub_#{signal}[#{i}].ready;
"
    end
    return str
end

#sub_inst ⇒ Object 



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# File 'lib/tdl/data_inf/bak/data_inf_interconnect.rb', line 50

def sub_inst
    return '' if @interconnect_up_streams.empty?
    if @interconnect_up_streams.first.is_a? Hash
        id_str = "logic [#{signal}.DSIZE-1:0]   #{signal}_sid   [#{@interconnect_up_streams.length-1}:0];\n"
    else
        id_str = ""
    end
    id_str+"data_inf #(.DSIZE(#{dsize}))  sub_#{signal} [#{@interconnect_up_streams.length-1}:0]();\n"+sub_direct
end

#to_data_inf_c(clock: nil, reset: nil) ⇒ Object 



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# File 'lib/tdl/elements/data_inf.rb', line 96

def to_data_inf_c(clock:nil,reset:nil)
    new_obj = belong_to_module.Def.datainf_c(name:@name+"_c",clock:clock,reset:reset,dsize:@dsize)
    belong_to_module.DataInf_C_draw << to_data_inf_c_draw(up_stream:self,down_stream:new_obj)
    return new_obj
end

#to_data_inf_c_draw(up_stream: nil, down_stream: nil) ⇒ Object 



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# File 'lib/tdl/elements/data_inf.rb', line 102

def to_data_inf_c_draw(up_stream:nil,down_stream:nil)
    large_name_len(up_stream,down_stream)
"data_inf_A2B data_inf_A2B_#{signal}_inst (
/*  data_inf.slaver   */  .slaver   (#{align_signal(up_stream)}),
/*  data_inf_c.master */  .master   (#{align_signal(down_stream)})
);"
end

#vld_rdy ⇒ Object

super(port_array,rep,“data_inf”,up_stream_rep) do |h|

    h[:type]   = DataInf
    yield h
end

end



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# File 'lib/tdl/rebuild_ele/data_inf.rb', line 23

def vld_rdy
    valid.concat(" && ").concat(ready)
end