Class: Axi4IllegalBFM

Inherits:
Axi4 show all
Defined in:
lib/tdl/bfm/axi4_illegal_bfm.rb

Constant Summary

Constants inherited from Axi4

Axi4::BOTH, Axi4::INTERFACE_S_SIGNALS, Axi4::INTERFACE_VECTOR_SIGNALS, Axi4::ONLY_READ, Axi4::ONLY_WRITE, Axi4::PORT_REP, Axi4::Synth_REP, Axi4::UP_STREAM_REP

Instance Attribute Summary

Attributes inherited from Axi4

#addr_step, #asize, #dsize, #ghost, #id, #idsize, #lsize, #mode, #name, #port

Attributes inherited from TdlSpace::TdlBaseInterface

#belong_to_module

Attributes included from TdlSpace::VarElemenCore

#dimension, #inst_name, #logic_type

Instance Method Summary collapse

Methods inherited from Axi4

#<<, #>>, #[], #__inf_signal__, #_axi4_combin_wr_rd_batch, #_axi4_combin_wr_rd_batch_draw, #_axi4_direct, #_axi4_direct_draw, #_axi4_direct_verb, #_axi4_direct_verb_draw, #_axi4_long_to_axi4_wide, #_axi4_long_to_axi4_wide_a1, #_axi4_long_to_axi4_wide_a1_draw, #_axi4_long_to_axi4_wide_draw, #_axi4_long_to_axi4_wide_verb, #_axi4_long_to_axi4_wide_verb_draw, #_axi4_to_native_for_ddr_ip_verb, #_axi4_to_native_for_ddr_ip_verb_draw, #_axi_data, #_odata_pool_axi4, #_odata_pool_axi4_a1, #_odata_pool_axi4_a1_draw, #_odata_pool_axi4_draw, axi4_combin_wr_rd_batch, #axi4_data_convert, axi4_data_convert, #axi4_data_convert_draw, #axi4_direct, axi4_direct, #axi4_direct_a1, axi4_direct_a1, #axi4_direct_draw, axi4_direct_verb, axi4_long_to_axi4_wide, axi4_long_to_axi4_wide_a1, axi4_long_to_axi4_wide_verb, axi4_packet_fifo, #axi4_packet_fifo, #axi4_packet_fifo_draw, axi4_partition_od, #axi4_partition_od, #axi4_partition_od_draw, axi4_pipe, #axi4_pipe, #axi4_pipe_draw, #axi4_pipe_verb, axi4_pipe_verb, axi4_to_native_for_ddr_ip_verb, #band_params_from, #branch, cal_addr_step, #clock_reset_taps, #ddr3, #ddr3_draw, #from_both, #from_only_read, #from_only_write, #from_video, #idata_pool_axi4, idata_pool_axi4, #idata_pool_axi4_draw, #inherited, #initialize, #inst, #inst_port, #interconnect_pipe=, odata_pool_axi4, odata_pool_axi4_a1, #old_append, parse_ports, same_name_socket, sync_mode, #sync_mode, #to_both, #to_iillegal_bfm, #to_only_read, #to_only_write, #to_video, #vcs_comptable, video_from_axi4, video_to_axi4, #video_to_vdma, video_to_vdma, #video_to_vdma_draw

Methods included from BaseFunc

#check_same, #check_same_class, #check_same_clock, #check_same_dsize

Methods included from BaseModule

#length, #to_s

Methods inherited from TdlSpace::TdlBaseInterface

#clock_reset_taps, #element_to_module, #force_name_copy, inherited, #initialize, #name_copy, parse_ports, #path_refs, subclass, #use_which_freq_when_copy

Methods included from TdlSpace::VarElemenAttr

#_io_map, #clock_io_map, #comm_io_map, #comm_io_maps_same, #gen_sv_interface, #get_class_var, #hdl_name, #modports, #param_map, #pdata_map, #reset_io_map, #sdata_maps, #set_class_var

Methods included from TdlSpace::VarElemenCore

#[], #_inner_inst, #inst_port, #instance, #modport_type, #modport_type=, #name, #name=, #to_s

Methods included from TdlSpace::ExCreateTP

#root_ref

Methods included from AxiTdl::TestUnitTrack

#tracked_by_dve

Constructor Details

This class inherits a constructor from Axi4

Instance Method Details

#exec(str = nil) ⇒ Object 



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# File 'lib/tdl/bfm/axi4_illegal_bfm.rb', line 78

def exec(str=nil)
    if block_given?
        ystr = yield(self)
        str = str.to_s + ystr
    end
    @_master_draw_exec_str_ << init_tap_draw("#{str.to_s};\n")
end

#init_exec(str) ⇒ Object 



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# File 'lib/tdl/bfm/axi4_illegal_bfm.rb', line 86

def init_exec(str)
    @_init_master_draw_exec_str_ ||= []
    @_init_master_draw_exec_str_ << init_tap_draw("#{str.to_s};\n")
end

#masterbfm(info: true, wdata_name: "wdata_queue") {|_self| ... } ⇒ Object

Yields:

  • (_self)

Yield Parameters:



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# File 'lib/tdl/bfm/axi4_illegal_bfm.rb', line 26

def masterbfm(info:true,wdata_name:"wdata_queue",&block)
    import_axibfm_pkg
    @wdata_name = wdata_name
    @_init_tap_cnt_ ||= 1
    @_master_draw_exec_str_ ||= []
    @_init_master_draw_exec_str_ ||= []
    # define_singleton_method(:wdata_queue) do
    #     "wdata_queue"
    # end

    yield self

    if info
        info_str = "ON"
    else
        info_str = "OFF"
    end
    belong_to_module.Axi4_draw << masterbfm_draw(info:info_str)

    return self
end

#masterbfm_draw(info: "OFF") ⇒ Object

def self.MasterBFM()

end



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# File 'lib/tdl/bfm/axi4_illegal_bfm.rb', line 52

def masterbfm_draw(info:"OFF")
    init_str = @_init_master_draw_exec_str_.join("")
    master_str = @_master_draw_exec_str_.join("")
"
Axi4IllMasterBfm_c #(
.IDSIZE    (#{@idsize}),
.ASIZE     (#{@asize}),
.LSIZE     (#{@lsize}),
.DSIZE     (#{@dsize}),
.MSG       (\"#{info}\"),
.ADDR_STEP (#{@addr_step.to_i})
) MasterIllBfm_#{signal};

initial begin:#{signal}_MASTER_ILLEGAL_BLOCK
logic [#{@dsize}-1:0]     #{@wdata_name}     [$];
axi4_illegal_s            illegal_s;
MasterIllBfm_#{signal} = new(#{signal});
MasterIllBfm_#{signal}.init();
#{init_str}
wait(#{signal}.axi_aresetn);
#{master_str}
end

"
end

#read_burst(addr: 0, len: 0, rate: 100, aw_off: false, last_off: false, ar_off: false, offset_len: 0, data: :random) ⇒ Object 



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# File 'lib/tdl/bfm/axi4_illegal_bfm.rb', line 157

def read_burst(addr:0,len:0,rate:100,aw_off:false,last_off:false,ar_off:false,offset_len:0,data: :random)
    f_to_bit = Proc.new do |v|
        if v
            1
        else
            0
        end
    end

    if data == :random
        data_str = %Q{
for(int i = 0;i<#{len};i++)begin
    #{@wdata_name}[i] = $urandom_range(0,#{len});
end}
     elsif data == :range
         data_str = %Q{
 for(int i = 0;i<#{len};i++)begin
     #{@wdata_name}[i] = i;
 end}
      else
          data_str = %Q{
  for(int i = 0;i<#{len};i++)begin
      #{@wdata_name}[i] = #{data.to_s};
  end}
       end

    @_master_draw_exec_str_ << %Q{
//--->> RESET STRICT <<--------------
    illegal_s.aw_off        = #{f_to_bit.call(aw_off)};
    illegal_s.ar_off        = #{f_to_bit.call(ar_off)};
    illegal_s.last_off      = #{f_to_bit.call(last_off)};
    illegal_s.offset_len    = #{offset_len};
//---<< RESET STRICT >>--------------
//--->> rdata data generate <<-------
#{data_str}
//---<< rdata data generate >>-------
}
    @_master_draw_exec_str_ << init_tap_draw("MasterIllBfm_#{signal}.read_burst(#{addr},#{len},#{rate},#{@wdata_name});\n")
end

#repeat(num = nil) {|_self| ... } ⇒ Object

def stream_exec(delay:“#(10us)”,str:“”)

@_master_draw_exec_str_ << "#(100ns) wdata_queue = #{str.to_s};\n"

end

Yields:

  • (_self)

Yield Parameters:



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# File 'lib/tdl/bfm/axi4_illegal_bfm.rb', line 95

def repeat(num=nil,&block)
    if num
        @_master_draw_exec_str_ << init_tap_draw("repeat(#{num}) begin\n")
    else
        @_master_draw_exec_str_ << init_tap_draw("forever begin\n")
    end
    @_init_tap_cnt_ += 1
    yield self
    @_init_tap_cnt_ -= 1
    @_master_draw_exec_str_ << init_tap_draw("end\n")
end

#wait(s, edge = nil) ⇒ Object 



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# File 'lib/tdl/bfm/axi4_illegal_bfm.rb', line 107

def wait(s,edge=nil)
    if edge.nil?
        @_master_draw_exec_str_ << init_tap_draw("wait(#{align_signal(s,q_mark=false)});\n")
    elsif edge.to_s.eql? "raising"
        @_master_draw_exec_str_ << init_tap_draw("@(posedge #{align_signal(s)});\n")
    elsif edge.to_s.eql? "falling"
        @_master_draw_exec_str_ << init_tap_draw("@(negedge #{align_signal(s)});\n")
    end
end

#write_burst(addr: 0, len: 0, rate: 100, aw_off: false, last_off: false, ar_off: false, offset_len: 0, data: :random) ⇒ Object 



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# File 'lib/tdl/bfm/axi4_illegal_bfm.rb', line 117

def write_burst(addr:0,len:0,rate:100,aw_off:false,last_off:false,ar_off:false,offset_len:0,data: :random)
    f_to_bit = Proc.new do |v|
        if v
            1
        else
            0
        end
    end

    if data == :random
        data_str = %Q{
for(int i = 0;i<#{len};i++)begin
    #{@wdata_name}[i] = $urandom_range(0,#{len});
end}
     elsif data == :range
         data_str = %Q{
 for(int i = 0;i<#{len};i++)begin
     #{@wdata_name}[i] = i;
 end}
      else
          data_str = %Q{
  for(int i = 0;i<#{len};i++)begin
      #{@wdata_name}[i] = #{data.to_s};
  end}
       end

    @_master_draw_exec_str_ << %Q{
//--->> RESET STRICT <<--------------
    illegal_s.aw_off        = #{f_to_bit.call(aw_off)};
    illegal_s.ar_off        = #{f_to_bit.call(ar_off)};
    illegal_s.last_off      = #{f_to_bit.call(last_off)};
    illegal_s.offset_len    = #{offset_len};
//---<< RESET STRICT >>--------------
//--->> wdata data generate <<-------
#{data_str}
//---<< wdata data generate >>-------
}
    @_master_draw_exec_str_ << init_tap_draw("MasterIllBfm_#{signal}.write_burst(illegal_s,#{addr},#{len},#{rate},#{@wdata_name});\n")
end